Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7896372 |
1 |
|
|
T25 |
1 |
|
T1 |
55630 |
|
T11 |
290 |
| auto[1] |
5734352 |
1 |
|
|
T1 |
40105 |
|
T13 |
207 |
|
T16 |
26661 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11249834 |
1 |
|
|
T25 |
1 |
|
T1 |
68349 |
|
T11 |
290 |
| auto[1] |
2380890 |
1 |
|
|
T1 |
27386 |
|
T13 |
173 |
|
T16 |
17635 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7897496 |
1 |
|
|
T25 |
1 |
|
T1 |
53483 |
|
T11 |
290 |
| auto[1] |
5733228 |
1 |
|
|
T1 |
42252 |
|
T13 |
183 |
|
T16 |
28502 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1675330 |
1 |
|
|
T1 |
7403 |
|
T13 |
10 |
|
T16 |
5726 |
| auto[1] |
auto[0] |
auto[1] |
1188093 |
1 |
|
|
T1 |
13929 |
|
T13 |
123 |
|
T16 |
8842 |
| auto[1] |
auto[1] |
auto[0] |
1677008 |
1 |
|
|
T1 |
7463 |
|
T16 |
5141 |
|
T19 |
91 |
| auto[1] |
auto[1] |
auto[1] |
1192797 |
1 |
|
|
T1 |
13457 |
|
T13 |
50 |
|
T16 |
8793 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |