Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870356 |
1 |
|
|
T25 |
1 |
|
T1 |
56340 |
|
T11 |
290 |
| auto[1] |
5760368 |
1 |
|
|
T1 |
39395 |
|
T13 |
307 |
|
T16 |
26501 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11248236 |
1 |
|
|
T25 |
1 |
|
T1 |
68432 |
|
T11 |
290 |
| auto[1] |
2382488 |
1 |
|
|
T1 |
27303 |
|
T13 |
244 |
|
T16 |
15865 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7898392 |
1 |
|
|
T25 |
1 |
|
T1 |
52659 |
|
T11 |
290 |
| auto[1] |
5732332 |
1 |
|
|
T1 |
43076 |
|
T13 |
324 |
|
T16 |
26196 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1663595 |
1 |
|
|
T1 |
8080 |
|
T13 |
39 |
|
T16 |
5551 |
| auto[1] |
auto[0] |
auto[1] |
1188952 |
1 |
|
|
T1 |
14170 |
|
T13 |
131 |
|
T16 |
8276 |
| auto[1] |
auto[1] |
auto[0] |
1686249 |
1 |
|
|
T1 |
7693 |
|
T13 |
41 |
|
T16 |
4780 |
| auto[1] |
auto[1] |
auto[1] |
1193536 |
1 |
|
|
T1 |
13133 |
|
T13 |
113 |
|
T16 |
7589 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |