Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7916088 |
1 |
|
|
T25 |
1 |
|
T1 |
55329 |
|
T11 |
290 |
| auto[1] |
5714636 |
1 |
|
|
T1 |
40406 |
|
T13 |
299 |
|
T16 |
28895 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11254687 |
1 |
|
|
T25 |
1 |
|
T1 |
70943 |
|
T11 |
290 |
| auto[1] |
2376037 |
1 |
|
|
T1 |
24792 |
|
T13 |
241 |
|
T16 |
17596 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906879 |
1 |
|
|
T25 |
1 |
|
T1 |
57087 |
|
T11 |
290 |
| auto[1] |
5723845 |
1 |
|
|
T1 |
38648 |
|
T13 |
299 |
|
T16 |
28259 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1681462 |
1 |
|
|
T1 |
7489 |
|
T13 |
19 |
|
T16 |
5216 |
| auto[1] |
auto[0] |
auto[1] |
1193477 |
1 |
|
|
T1 |
13644 |
|
T13 |
143 |
|
T16 |
8454 |
| auto[1] |
auto[1] |
auto[0] |
1666346 |
1 |
|
|
T1 |
6367 |
|
T13 |
39 |
|
T16 |
5447 |
| auto[1] |
auto[1] |
auto[1] |
1182560 |
1 |
|
|
T1 |
11148 |
|
T13 |
98 |
|
T16 |
9142 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |