Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884245 |
1 |
|
|
T25 |
1 |
|
T1 |
57278 |
|
T11 |
290 |
| auto[1] |
5746479 |
1 |
|
|
T1 |
38457 |
|
T13 |
249 |
|
T16 |
28526 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11243698 |
1 |
|
|
T25 |
1 |
|
T1 |
68791 |
|
T11 |
290 |
| auto[1] |
2387026 |
1 |
|
|
T1 |
26944 |
|
T13 |
341 |
|
T16 |
16258 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7885509 |
1 |
|
|
T25 |
1 |
|
T1 |
53995 |
|
T11 |
290 |
| auto[1] |
5745215 |
1 |
|
|
T1 |
41740 |
|
T13 |
391 |
|
T16 |
26304 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1670539 |
1 |
|
|
T1 |
7812 |
|
T13 |
34 |
|
T16 |
4805 |
| auto[1] |
auto[0] |
auto[1] |
1186929 |
1 |
|
|
T1 |
14424 |
|
T13 |
183 |
|
T16 |
7636 |
| auto[1] |
auto[1] |
auto[0] |
1687650 |
1 |
|
|
T1 |
6984 |
|
T13 |
16 |
|
T16 |
5241 |
| auto[1] |
auto[1] |
auto[1] |
1200097 |
1 |
|
|
T1 |
12520 |
|
T13 |
158 |
|
T16 |
8622 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |