Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7868164 |
1 |
|
|
T25 |
1 |
|
T1 |
52590 |
|
T11 |
290 |
| auto[1] |
5762560 |
1 |
|
|
T1 |
43145 |
|
T13 |
283 |
|
T16 |
28616 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12901119 |
1 |
|
|
T25 |
1 |
|
T1 |
91072 |
|
T11 |
290 |
| auto[1] |
729605 |
1 |
|
|
T1 |
4663 |
|
T13 |
9 |
|
T16 |
3176 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910851 |
1 |
|
|
T25 |
1 |
|
T1 |
55329 |
|
T11 |
290 |
| auto[1] |
5719873 |
1 |
|
|
T1 |
40406 |
|
T13 |
292 |
|
T16 |
27563 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2499924 |
1 |
|
|
T1 |
17843 |
|
T13 |
146 |
|
T16 |
12281 |
| auto[1] |
auto[0] |
auto[1] |
364982 |
1 |
|
|
T1 |
2371 |
|
T13 |
5 |
|
T16 |
1701 |
| auto[1] |
auto[1] |
auto[0] |
2490344 |
1 |
|
|
T1 |
17900 |
|
T13 |
137 |
|
T16 |
12106 |
| auto[1] |
auto[1] |
auto[1] |
364623 |
1 |
|
|
T1 |
2292 |
|
T13 |
4 |
|
T16 |
1475 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |