Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7874343 |
1 |
|
|
T25 |
1 |
|
T1 |
53584 |
|
T11 |
290 |
| auto[1] |
5756381 |
1 |
|
|
T1 |
42151 |
|
T13 |
259 |
|
T16 |
29138 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12896729 |
1 |
|
|
T25 |
1 |
|
T1 |
90900 |
|
T11 |
290 |
| auto[1] |
733995 |
1 |
|
|
T1 |
4835 |
|
T13 |
11 |
|
T16 |
3238 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7888813 |
1 |
|
|
T25 |
1 |
|
T1 |
54632 |
|
T11 |
290 |
| auto[1] |
5741911 |
1 |
|
|
T1 |
41103 |
|
T13 |
283 |
|
T16 |
27825 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2502625 |
1 |
|
|
T1 |
16987 |
|
T13 |
158 |
|
T16 |
11763 |
| auto[1] |
auto[0] |
auto[1] |
367482 |
1 |
|
|
T1 |
2282 |
|
T13 |
4 |
|
T16 |
1526 |
| auto[1] |
auto[1] |
auto[0] |
2505291 |
1 |
|
|
T1 |
19281 |
|
T13 |
114 |
|
T16 |
12824 |
| auto[1] |
auto[1] |
auto[1] |
366513 |
1 |
|
|
T1 |
2553 |
|
T13 |
7 |
|
T16 |
1712 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |