Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7899601 |
1 |
|
|
T25 |
1 |
|
T1 |
54850 |
|
T11 |
290 |
| auto[1] |
5731123 |
1 |
|
|
T1 |
40885 |
|
T13 |
218 |
|
T16 |
28521 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12902854 |
1 |
|
|
T25 |
1 |
|
T1 |
90992 |
|
T11 |
290 |
| auto[1] |
727870 |
1 |
|
|
T1 |
4743 |
|
T13 |
7 |
|
T16 |
3610 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7923296 |
1 |
|
|
T25 |
1 |
|
T1 |
55991 |
|
T11 |
290 |
| auto[1] |
5707428 |
1 |
|
|
T1 |
39744 |
|
T13 |
247 |
|
T16 |
29607 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2498414 |
1 |
|
|
T1 |
17849 |
|
T13 |
148 |
|
T16 |
12901 |
| auto[1] |
auto[0] |
auto[1] |
365245 |
1 |
|
|
T1 |
2404 |
|
T13 |
3 |
|
T16 |
1851 |
| auto[1] |
auto[1] |
auto[0] |
2481144 |
1 |
|
|
T1 |
17152 |
|
T13 |
92 |
|
T16 |
13096 |
| auto[1] |
auto[1] |
auto[1] |
362625 |
1 |
|
|
T1 |
2339 |
|
T13 |
4 |
|
T16 |
1759 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |