Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878568 |
1 |
|
|
T25 |
1 |
|
T1 |
51709 |
|
T11 |
290 |
| auto[1] |
5752156 |
1 |
|
|
T1 |
44026 |
|
T13 |
199 |
|
T16 |
27569 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12894454 |
1 |
|
|
T25 |
1 |
|
T1 |
90994 |
|
T11 |
290 |
| auto[1] |
736270 |
1 |
|
|
T1 |
4741 |
|
T13 |
9 |
|
T16 |
2911 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7865161 |
1 |
|
|
T25 |
1 |
|
T1 |
54761 |
|
T11 |
290 |
| auto[1] |
5765563 |
1 |
|
|
T1 |
40974 |
|
T13 |
230 |
|
T16 |
26159 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2516463 |
1 |
|
|
T1 |
17437 |
|
T13 |
128 |
|
T16 |
11723 |
| auto[1] |
auto[0] |
auto[1] |
369081 |
1 |
|
|
T1 |
2307 |
|
T13 |
7 |
|
T16 |
1495 |
| auto[1] |
auto[1] |
auto[0] |
2512830 |
1 |
|
|
T1 |
18796 |
|
T13 |
93 |
|
T16 |
11525 |
| auto[1] |
auto[1] |
auto[1] |
367189 |
1 |
|
|
T1 |
2434 |
|
T13 |
2 |
|
T16 |
1416 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |