Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7903310 |
1 |
|
|
T25 |
1 |
|
T1 |
55381 |
|
T11 |
290 |
| auto[1] |
5727414 |
1 |
|
|
T1 |
40354 |
|
T13 |
349 |
|
T16 |
28797 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12894678 |
1 |
|
|
T25 |
1 |
|
T1 |
90606 |
|
T11 |
290 |
| auto[1] |
736046 |
1 |
|
|
T1 |
5129 |
|
T13 |
12 |
|
T16 |
3385 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7874979 |
1 |
|
|
T25 |
1 |
|
T1 |
53624 |
|
T11 |
290 |
| auto[1] |
5755745 |
1 |
|
|
T1 |
42111 |
|
T13 |
273 |
|
T16 |
28198 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2512711 |
1 |
|
|
T1 |
18280 |
|
T13 |
149 |
|
T16 |
11408 |
| auto[1] |
auto[0] |
auto[1] |
369028 |
1 |
|
|
T1 |
2547 |
|
T13 |
8 |
|
T16 |
1532 |
| auto[1] |
auto[1] |
auto[0] |
2506988 |
1 |
|
|
T1 |
18702 |
|
T13 |
112 |
|
T16 |
13405 |
| auto[1] |
auto[1] |
auto[1] |
367018 |
1 |
|
|
T1 |
2582 |
|
T13 |
4 |
|
T16 |
1853 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |