Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3664791	1			T23	1		T24	159		T25	1
all_pins[1]	3664791	1			T23	1		T24	159		T25	1
all_pins[2]	3664791	1			T23	1		T24	159		T25	1
all_pins[3]	3664791	1			T23	1		T24	159		T25	1
all_pins[4]	3664791	1			T23	1		T24	159		T25	1
all_pins[5]	3664791	1			T23	1		T24	159		T25	1
all_pins[6]	3664791	1			T23	1		T24	159		T25	1
all_pins[7]	3664791	1			T23	1		T24	159		T25	1
all_pins[8]	3664791	1			T23	1		T24	159		T25	1
all_pins[9]	3664791	1			T23	1		T24	159		T25	1
all_pins[10]	3664791	1			T23	1		T24	159		T25	1
all_pins[11]	3664791	1			T23	1		T24	159		T25	1
all_pins[12]	3664791	1			T23	1		T24	159		T25	1
all_pins[13]	3664791	1			T23	1		T24	159		T25	1
all_pins[14]	3664791	1			T23	1		T24	159		T25	1
all_pins[15]	3664791	1			T23	1		T24	159		T25	1
all_pins[16]	3664791	1			T23	1		T24	159		T25	1
all_pins[17]	3664791	1			T23	1		T24	159		T25	1
all_pins[18]	3664791	1			T23	1		T24	159		T25	1
all_pins[19]	3664791	1			T23	1		T24	159		T25	1
all_pins[20]	3664791	1			T23	1		T24	159		T25	1
all_pins[21]	3664791	1			T23	1		T24	159		T25	1
all_pins[22]	3664791	1			T23	1		T24	159		T25	1
all_pins[23]	3664791	1			T23	1		T24	159		T25	1
all_pins[24]	3664791	1			T23	1		T24	159		T25	1
all_pins[25]	3664791	1			T23	1		T24	159		T25	1
all_pins[26]	3664791	1			T23	1		T24	159		T25	1
all_pins[27]	3664791	1			T23	1		T24	159		T25	1
all_pins[28]	3664791	1			T23	1		T24	159		T25	1
all_pins[29]	3664791	1			T23	1		T24	159		T25	1
all_pins[30]	3664791	1			T23	1		T24	159		T25	1
all_pins[31]	3664791	1			T23	1		T24	159		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	72833839	1			T23	32		T24	3288		T25	32
values[0x1]	44439473	1			T24	1800		T1	652		T11	154507
transitions[0x0=>0x1]	26617636	1			T24	1111		T1	387		T11	924584
transitions[0x1=>0x0]	26617474	1			T24	1111		T1	387		T11	924584

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2275055	1			T23	1		T24	132		T25	1
all_pins[0]	values[0x1]	1389736	1			T24	27		T1	10		T11	49046
all_pins[0]	transitions[0x0=>0x1]	858998	1			T24	16		T1	7		T11	30294
all_pins[0]	transitions[0x1=>0x0]	861001	1			T24	55		T1	22		T11	29856
all_pins[1]	values[0x0]	2270519	1			T23	1		T24	114		T25	1
all_pins[1]	values[0x1]	1394272	1			T24	45		T1	23		T11	48551
all_pins[1]	transitions[0x0=>0x1]	833565	1			T24	39		T1	16		T11	28864
all_pins[1]	transitions[0x1=>0x0]	829029	1			T24	21		T1	3		T11	29359
all_pins[2]	values[0x0]	2277309	1			T23	1		T24	113		T25	1
all_pins[2]	values[0x1]	1387482	1			T24	46		T1	33		T11	48659
all_pins[2]	transitions[0x0=>0x1]	828239	1			T24	24		T1	22		T11	28836
all_pins[2]	transitions[0x1=>0x0]	835029	1			T24	23		T1	12		T11	28728
all_pins[3]	values[0x0]	2272436	1			T23	1		T24	84		T25	1
all_pins[3]	values[0x1]	1392355	1			T24	75		T1	42		T11	47766
all_pins[3]	transitions[0x0=>0x1]	832363	1			T24	58		T1	12		T11	29046
all_pins[3]	transitions[0x1=>0x0]	827490	1			T24	29		T1	3		T11	29939
all_pins[4]	values[0x0]	2274536	1			T23	1		T24	121		T25	1
all_pins[4]	values[0x1]	1390255	1			T24	38		T1	10		T11	47437
all_pins[4]	transitions[0x0=>0x1]	829770	1			T24	16		T1	5		T11	28436
all_pins[4]	transitions[0x1=>0x0]	831870	1			T24	53		T1	37		T11	28765
all_pins[5]	values[0x0]	2277864	1			T23	1		T24	101		T25	1
all_pins[5]	values[0x1]	1386927	1			T24	58		T1	12		T11	48822
all_pins[5]	transitions[0x0=>0x1]	828676	1			T24	41		T1	7		T11	29680
all_pins[5]	transitions[0x1=>0x0]	832004	1			T24	21		T1	5		T11	28295
all_pins[6]	values[0x0]	2275686	1			T23	1		T24	85		T25	1
all_pins[6]	values[0x1]	1389105	1			T24	74		T1	11		T11	48422
all_pins[6]	transitions[0x0=>0x1]	832109	1			T24	47		T1	6		T11	28737
all_pins[6]	transitions[0x1=>0x0]	829931	1			T24	31		T1	7		T11	29137
all_pins[7]	values[0x0]	2278460	1			T23	1		T24	107		T25	1
all_pins[7]	values[0x1]	1386331	1			T24	52		T1	12		T11	48728
all_pins[7]	transitions[0x0=>0x1]	830277	1			T24	30		T1	10		T11	29420
all_pins[7]	transitions[0x1=>0x0]	833051	1			T24	52		T1	9		T11	29114
all_pins[8]	values[0x0]	2279521	1			T23	1		T24	98		T25	1
all_pins[8]	values[0x1]	1385270	1			T24	61		T1	29		T11	47995
all_pins[8]	transitions[0x0=>0x1]	828134	1			T24	42		T1	27		T11	28355
all_pins[8]	transitions[0x1=>0x0]	829195	1			T24	33		T1	10		T11	29088
all_pins[9]	values[0x0]	2273583	1			T23	1		T24	95		T25	1
all_pins[9]	values[0x1]	1391208	1			T24	64		T1	12		T11	48207
all_pins[9]	transitions[0x0=>0x1]	833943	1			T24	33		T1	1		T11	28884
all_pins[9]	transitions[0x1=>0x0]	828005	1			T24	30		T1	18		T11	28672
all_pins[10]	values[0x0]	2279625	1			T23	1		T24	103		T25	1
all_pins[10]	values[0x1]	1385166	1			T24	56		T1	24		T11	49339
all_pins[10]	transitions[0x0=>0x1]	829425	1			T24	26		T1	15		T11	29531
all_pins[10]	transitions[0x1=>0x0]	835467	1			T24	34		T1	3		T11	28399
all_pins[11]	values[0x0]	2278813	1			T23	1		T24	89		T25	1
all_pins[11]	values[0x1]	1385978	1			T24	70		T1	12		T11	48399
all_pins[11]	transitions[0x0=>0x1]	831416	1			T24	43		T1	1		T11	28378
all_pins[11]	transitions[0x1=>0x0]	830604	1			T24	29		T1	13		T11	29318
all_pins[12]	values[0x0]	2277006	1			T23	1		T24	69		T25	1
all_pins[12]	values[0x1]	1387785	1			T24	90		T1	28		T11	48296
all_pins[12]	transitions[0x0=>0x1]	830378	1			T24	50		T1	21		T11	28984
all_pins[12]	transitions[0x1=>0x0]	828571	1			T24	30		T1	5		T11	29087
all_pins[13]	values[0x0]	2275043	1			T23	1		T24	96		T25	1
all_pins[13]	values[0x1]	1389748	1			T24	63		T1	14		T11	48288
all_pins[13]	transitions[0x0=>0x1]	832646	1			T24	31		T1	11		T11	28798
all_pins[13]	transitions[0x1=>0x0]	830683	1			T24	58		T1	25		T11	28806
all_pins[14]	values[0x0]	2276502	1			T23	1		T24	83		T25	1
all_pins[14]	values[0x1]	1388289	1			T24	76		T1	28		T11	47865
all_pins[14]	transitions[0x0=>0x1]	831890	1			T24	50		T1	21		T11	28669
all_pins[14]	transitions[0x1=>0x0]	833349	1			T24	37		T1	7		T11	29092
all_pins[15]	values[0x0]	2276287	1			T23	1		T24	121		T25	1
all_pins[15]	values[0x1]	1388504	1			T24	38		T1	16		T11	49092
all_pins[15]	transitions[0x0=>0x1]	828083	1			T24	7		T1	11		T11	29367
all_pins[15]	transitions[0x1=>0x0]	827868	1			T24	45		T1	23		T11	28140
all_pins[16]	values[0x0]	2278060	1			T23	1		T24	114		T25	1
all_pins[16]	values[0x1]	1386731	1			T24	45		T1	27		T11	48658
all_pins[16]	transitions[0x0=>0x1]	828216	1			T24	33		T1	22		T11	28477
all_pins[16]	transitions[0x1=>0x0]	829989	1			T24	26		T1	11		T11	28911
all_pins[17]	values[0x0]	2278694	1			T23	1		T24	96		T25	1
all_pins[17]	values[0x1]	1386097	1			T24	63		T1	11		T11	48209
all_pins[17]	transitions[0x0=>0x1]	830085	1			T24	47		T1	10		T11	28528
all_pins[17]	transitions[0x1=>0x0]	830719	1			T24	29		T1	26		T11	28977
all_pins[18]	values[0x0]	2270829	1			T23	1		T24	93		T25	1
all_pins[18]	values[0x1]	1393962	1			T24	66		T1	13		T11	47316
all_pins[18]	transitions[0x0=>0x1]	837376	1			T24	36		T1	7		T11	28210
all_pins[18]	transitions[0x1=>0x0]	829511	1			T24	33		T1	5		T11	29103
all_pins[19]	values[0x0]	2275409	1			T23	1		T24	81		T25	1
all_pins[19]	values[0x1]	1389382	1			T24	78		T1	21		T11	47646
all_pins[19]	transitions[0x0=>0x1]	830911	1			T24	36		T1	18		T11	28672
all_pins[19]	transitions[0x1=>0x0]	835491	1			T24	24		T1	10		T11	28342
all_pins[20]	values[0x0]	2277355	1			T23	1		T24	112		T25	1
all_pins[20]	values[0x1]	1387436	1			T24	47		T1	23		T11	49262
all_pins[20]	transitions[0x0=>0x1]	831628	1			T24	20		T1	16		T11	29921
all_pins[20]	transitions[0x1=>0x0]	833574	1			T24	51		T1	14		T11	28305
all_pins[21]	values[0x0]	2278173	1			T23	1		T24	105		T25	1
all_pins[21]	values[0x1]	1386618	1			T24	54		T1	16		T11	48735
all_pins[21]	transitions[0x0=>0x1]	828707	1			T24	44		T1	4		T11	28692
all_pins[21]	transitions[0x1=>0x0]	829525	1			T24	37		T1	11		T11	29219
all_pins[22]	values[0x0]	2277202	1			T23	1		T24	108		T25	1
all_pins[22]	values[0x1]	1387589	1			T24	51		T1	36		T11	48539
all_pins[22]	transitions[0x0=>0x1]	830113	1			T24	26		T1	23		T11	28606
all_pins[22]	transitions[0x1=>0x0]	829142	1			T24	29		T1	3		T11	28802
all_pins[23]	values[0x0]	2269036	1			T23	1		T24	127		T25	1
all_pins[23]	values[0x1]	1395755	1			T24	32		T1	43		T11	48047
all_pins[23]	transitions[0x0=>0x1]	834241	1			T24	21		T1	9		T11	28427
all_pins[23]	transitions[0x1=>0x0]	826075	1			T24	40		T1	2		T11	28919
all_pins[24]	values[0x0]	2275457	1			T23	1		T24	95		T25	1
all_pins[24]	values[0x1]	1389334	1			T24	64		T1	16		T11	48264
all_pins[24]	transitions[0x0=>0x1]	830236	1			T24	48		T1	5		T11	29246
all_pins[24]	transitions[0x1=>0x0]	836657	1			T24	16		T1	32		T11	29029
all_pins[25]	values[0x0]	2278359	1			T23	1		T24	108		T25	1
all_pins[25]	values[0x1]	1386432	1			T24	51		T1	13		T11	48242
all_pins[25]	transitions[0x0=>0x1]	830121	1			T24	34		T1	7		T11	28981
all_pins[25]	transitions[0x1=>0x0]	833023	1			T24	47		T1	10		T11	29003
all_pins[26]	values[0x0]	2275245	1			T23	1		T24	96		T25	1
all_pins[26]	values[0x1]	1389546	1			T24	63		T1	7		T11	47209
all_pins[26]	transitions[0x0=>0x1]	832438	1			T24	37		T1	3		T11	28413
all_pins[26]	transitions[0x1=>0x0]	829324	1			T24	25		T1	9		T11	29446
all_pins[27]	values[0x0]	2270633	1			T23	1		T24	115		T25	1
all_pins[27]	values[0x1]	1394158	1			T24	44		T1	25		T11	47579
all_pins[27]	transitions[0x0=>0x1]	832319	1			T24	26		T1	24		T11	28474
all_pins[27]	transitions[0x1=>0x0]	827707	1			T24	45		T1	6		T11	28104
all_pins[28]	values[0x0]	2277267	1			T23	1		T24	110		T25	1
all_pins[28]	values[0x1]	1387524	1			T24	49		T1	19		T11	47504
all_pins[28]	transitions[0x0=>0x1]	827837	1			T24	27		T1	9		T11	28730
all_pins[28]	transitions[0x1=>0x0]	834471	1			T24	22		T1	15		T11	28805
all_pins[29]	values[0x0]	2278643	1			T23	1		T24	110		T25	1
all_pins[29]	values[0x1]	1386148	1			T24	49		T1	17		T11	48687
all_pins[29]	transitions[0x0=>0x1]	829172	1			T24	32		T1	8		T11	29291
all_pins[29]	transitions[0x1=>0x0]	830548	1			T24	32		T1	10		T11	28108
all_pins[30]	values[0x0]	2282342	1			T23	1		T24	114		T25	1
all_pins[30]	values[0x1]	1382449	1			T24	45		T1	24		T11	47659
all_pins[30]	transitions[0x0=>0x1]	826994	1			T24	35		T1	11		T11	28698
all_pins[30]	transitions[0x1=>0x0]	830693	1			T24	39		T1	4		T11	29726
all_pins[31]	values[0x0]	2272890	1			T23	1		T24	93		T25	1
all_pins[31]	values[0x1]	1391901	1			T24	66		T1	25		T11	48608
all_pins[31]	transitions[0x0=>0x1]	837330	1			T24	56		T1	18		T11	28939
all_pins[31]	transitions[0x1=>0x0]	827878	1			T24	35		T1	17		T11	27990