Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[1]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[2]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[3]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[4]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[5]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[6]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[7]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[8]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[9]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[10]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[11]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[12]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[13]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[14]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[15]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[16]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[17]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[18]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[19]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[20]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[21]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[22]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[23]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[24]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[25]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[26]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[27]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[28]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[29]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[30]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[31]	12452577	1			T23	231		T24	117		T25	504

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235014869

1

T23

5822

T24

1811

T25

3523

auto[1]

163467595

1

T23

1570

T24

1933

T25

12605

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319915335

1

T23

4979

T24

3744

T25

12428

auto[1]

78567129

1

T23

2413

T25

3700

T26

2865

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297062328

1

T23

3756

T24

3744

T25

7485

auto[1]

101420136

1

T23

3636

T25

8643

T26

2930

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4597223	1			T23	73		T24	57		T25	28
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3453318	1			T23	12		T24	60		T25	125
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1237336	1			T23	80		T25	19		T26	24
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1521623	1			T23	46		T25	35		T26	60
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	425734	1			T23	1		T25	214		T1	31
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1217343	1			T23	19		T25	83		T26	44
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4582433	1			T23	71		T24	48		T25	32
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3463144	1			T23	10		T24	69		T25	157
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1237567	1			T23	47		T25	65		T26	51
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1518293	1			T23	83		T25	18		T26	42
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	428283	1			T23	3		T25	165		T1	84
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1222857	1			T23	17		T25	67		T26	38
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4578330	1			T23	35		T24	52		T25	22
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3470397	1			T23	3		T24	65		T25	174
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1233950	1			T23	27		T25	62		T26	34
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1523436	1			T23	92		T25	35		T26	56
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	423373	1			T23	14		T25	134		T1	28
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1223091	1			T23	60		T25	77		T26	63
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4594914	1			T23	26		T24	52		T25	16
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3459668	1			T23	8		T24	65		T25	101
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1234560	1			T23	35		T25	49		T26	32
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1514032	1			T23	94		T25	51		T26	34
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	425926	1			T23	7		T25	213		T1	83
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1223477	1			T23	61		T25	74		T26	77
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4586000	1			T23	41		T24	49		T25	43
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3457709	1			T23	7		T24	68		T25	150
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1238830	1			T23	36		T25	76		T26	49
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1518337	1			T23	113		T25	20		T26	48
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	425061	1			T23	9		T25	158		T1	75
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1226640	1			T23	25		T25	57		T26	48
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4584802	1			T23	44		T24	46		T25	23
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3456043	1			T23	3		T24	71		T25	149
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1233115	1			T23	30		T25	60		T26	69
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1527257	1			T23	86		T25	35		T26	24
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	426959	1			T23	11		T25	176		T1	46
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1224401	1			T23	57		T25	61		T26	52
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4583999	1			T23	78		T24	64		T25	23
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3464641	1			T23	7		T24	53		T25	155
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1237530	1			T23	49		T25	48		T26	42
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1517308	1			T23	52		T25	37		T26	60
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	424916	1			T23	11		T25	198		T1	28
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1224183	1			T23	34		T25	43		T26	35
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4592193	1			T23	56		T24	51		T25	18
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3460635	1			T23	1		T24	66		T25	168
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1231240	1			T23	45		T25	50		T26	26
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1522205	1			T23	80		T25	33		T26	68
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	424827	1			T23	8		T25	187		T1	65
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1221477	1			T23	41		T25	48		T26	39
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4582838	1			T23	124		T24	56		T25	15
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3468844	1			T23	8		T24	61		T25	123
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1235959	1			T23	80		T25	46		T26	40
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1516738	1			T23	16		T25	43		T26	46
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	424575	1			T25	204		T1	51		T11	4263
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1223623	1			T23	3		T25	73		T26	45
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4582207	1			T23	94		T24	63		T25	17
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3464711	1			T23	11		T24	54		T25	129
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1233754	1			T23	46		T25	34		T26	52
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1519003	1			T23	47		T25	35		T26	40
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	426782	1			T23	3		T25	221		T1	11
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1226120	1			T23	30		T25	68		T26	44
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4590662	1			T23	38		T24	58		T25	30
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3458019	1			T23	3		T24	59		T25	124
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1235511	1			T23	19		T25	45		T26	50
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1523851	1			T23	113		T25	37		T26	38
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	425617	1			T23	15		T25	185		T1	50
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1218917	1			T23	43		T25	83		T26	42
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4588158	1			T23	108		T24	59		T25	34
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3461038	1			T23	8		T24	58		T25	212
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1235600	1			T23	34		T25	64		T26	54
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1518295	1			T23	40		T25	24		T26	45
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	424331	1			T23	4		T25	126		T1	50
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1225155	1			T23	37		T25	44		T26	42
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4590957	1			T23	75		T24	68		T25	32
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3455186	1			T23	12		T24	49		T25	165
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1237061	1			T23	12		T25	48		T26	40
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1522275	1			T23	92		T25	24		T26	50
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	424562	1			T23	6		T25	176		T1	55
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1222536	1			T23	34		T25	59		T26	45
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4587472	1			T23	52		T24	59		T25	23
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3460059	1			T23	8		T24	58		T25	156
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1232770	1			T23	53		T25	65		T26	34
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1522484	1			T23	69		T25	22		T26	48
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	424963	1			T23	9		T25	170		T1	70
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1224829	1			T23	40		T25	68		T26	43
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4578219	1			T23	98		T24	59		T25	32
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3465174	1			T23	7		T24	58		T25	159
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1236846	1			T23	57		T25	52		T26	28
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1523384	1			T23	39		T25	38		T26	51
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	425943	1			T23	5		T25	153		T1	49
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1223011	1			T23	25		T25	70		T26	36
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4591720	1			T23	61		T24	59		T25	24
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3461560	1			T23	4		T24	58		T25	128
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1232287	1			T23	34		T25	45		T26	66
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1516283	1			T23	68		T25	27		T26	44
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	426862	1			T23	10		T25	186		T1	62
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1223865	1			T23	54		T25	94		T26	23
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4601398	1			T23	63		T24	50		T25	24
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3453959	1			T23	6		T24	67		T25	177
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1232840	1			T23	41		T25	55		T26	54
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1520985	1			T23	69		T25	42		T26	48
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	424946	1			T23	12		T25	164		T1	30
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1218449	1			T23	40		T25	42		T26	43
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4586578	1			T23	62		T24	47		T25	22
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3461623	1			T23	5		T24	70		T25	82
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1234928	1			T23	22		T25	32		T26	44
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1522087	1			T23	101		T25	40		T26	40
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	426618	1			T23	10		T25	243		T1	28
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1220743	1			T23	31		T25	85		T26	52
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4594546	1			T23	67		T24	51		T25	43
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3451620	1			T23	5		T24	66		T25	224
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1231341	1			T23	53		T25	51		T26	67
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1523777	1			T23	63		T25	19		T26	34
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	427962	1			T23	11		T25	130		T1	45
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1223331	1			T23	32		T25	37		T26	38
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4595438	1			T23	111		T24	61		T25	33
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3458742	1			T23	12		T24	56		T25	208
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1235163	1			T23	70		T25	79		T26	66
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1521786	1			T23	22		T25	15		T26	40
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	427088	1			T23	1		T25	119		T1	56
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1214360	1			T23	15		T25	50		T26	39
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4582395	1			T23	92		T24	57		T25	26
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3462069	1			T23	6		T24	60		T25	135
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1230869	1			T23	51		T25	33		T26	33
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1525217	1			T23	61		T25	29		T26	72
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	425689	1			T23	3		T25	217		T1	67
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1226338	1			T23	18		T25	64		T26	48
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4587860	1			T23	70		T24	50		T25	12
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3463752	1			T23	4		T24	67		T25	109
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1231166	1			T23	23		T25	58		T26	50
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1526484	1			T23	84		T25	38		T26	40
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	423848	1			T23	8		T25	198		T1	51
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1219467	1			T23	42		T25	89		T26	43
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4583126	1			T23	115		T24	70		T25	22
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3466791	1			T23	10		T24	47		T25	144
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1229386	1			T23	41		T25	53		T26	44
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1523593	1			T23	56		T25	37		T26	46
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	423843	1			T23	3		T25	169		T1	55
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1225838	1			T23	6		T25	79		T26	49
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4590976	1			T23	76		T24	70		T25	15
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3458578	1			T23	9		T24	47		T25	147
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1236481	1			T23	52		T25	48		T26	42
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1523362	1			T23	40		T25	29		T26	44
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	424361	1			T23	7		T25	198		T1	81
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1218819	1			T23	47		T25	67		T26	39
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4582214	1			T23	26		T24	59		T25	49
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3470710	1			T23	1		T24	58		T25	205
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1232671	1			T23	30		T25	66		T26	53
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1524103	1			T23	99		T25	13		T26	24
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	426023	1			T23	13		T25	115		T1	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1216856	1			T23	62		T25	56		T26	64
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4593446	1			T23	90		T24	58		T25	49
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3454967	1			T23	7		T24	59		T25	196
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1227616	1			T23	33		T25	82		T26	40
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1526334	1			T23	69		T25	20		T26	47
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	429323	1			T23	6		T25	126		T1	20
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1220891	1			T23	26		T25	31		T26	64
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4593575	1			T23	34		T24	57		T25	34
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3462427	1			T23	3		T24	60		T25	170
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1233431	1			T23	46		T25	49		T26	62
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1525090	1			T23	88		T25	28		T26	41
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	424345	1			T23	11		T25	159		T1	66
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1213709	1			T23	49		T25	64		T26	26
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4584136	1			T23	81		T24	52		T25	7
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3468512	1			T23	8		T24	65		T25	119
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1232554	1			T23	6		T25	25		T26	48
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1522834	1			T23	97		T25	47		T26	52
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	427203	1			T23	7		T25	229		T1	69
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1217338	1			T23	32		T25	77		T26	36
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4594541	1			T23	38		T24	53		T25	31
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3463515	1			T23	7		T24	64		T25	217
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1234514	1			T23	64		T25	70		T26	36
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1520105	1			T23	73		T25	33		T26	67
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	422547	1			T23	8		T25	109		T1	55
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1217355	1			T23	41		T25	44		T26	40
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4583860	1			T23	83		T24	62		T25	37
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3464534	1			T23	7		T24	55		T25	177
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1229246	1			T23	32		T25	59		T26	36
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1527452	1			T23	77		T25	31		T26	60
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	429348	1			T23	6		T25	145		T1	29
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1218137	1			T23	26		T25	55		T26	36
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4599220	1			T23	86		T24	64		T25	32
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3449370	1			T23	5		T24	53		T25	152
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1228339	1			T23	30		T25	40		T26	31
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1527373	1			T23	56		T25	26		T26	42
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	425608	1			T23	7		T25	181		T1	30
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1222667	1			T23	47		T25	73		T26	58
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4586324	1			T23	78		T24	50		T25	13
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3462616	1			T23	6		T24	67		T25	128
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1232176	1			T23	19		T25	31		T26	47
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1521086	1			T23	94		T25	42		T26	58
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	425706	1			T23	12		T25	231		T1	18
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1224669	1			T23	22		T25	59		T26	30

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal