Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[1]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[2]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[3]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[4]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[5]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[6]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[7]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[8]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[9]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[10]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[11]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[12]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[13]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[14]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[15]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[16]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[17]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[18]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[19]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[20]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[21]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[22]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[23]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[24]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[25]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[26]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[27]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[28]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[29]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[30]	12452577	1			T23	231		T24	117		T25	504
bins_for_gpio_bits[31]	12452577	1			T23	231		T24	117		T25	504

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235014869

1

T23

5822

T24

1811

T25

3523

auto[1]

163467595

1

T23

1570

T24

1933

T25

12605

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

235007565

1

T23

5814

T24

1811

T25

3533

auto[1]

163474899

1

T23

1578

T24

1933

T25

12595

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7136784	1			T23	195		T24	57		T25	78
bins_for_gpio_bits[0]	auto[0]	auto[1]	219196	1			T23	4		T25	5		T26	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	219398	1			T23	4		T25	4		T26	9
bins_for_gpio_bits[0]	auto[1]	auto[1]	4877199	1			T23	28		T24	60		T25	417
bins_for_gpio_bits[1]	auto[0]	auto[0]	7118738	1			T23	197		T24	48		T25	101
bins_for_gpio_bits[1]	auto[0]	auto[1]	219348	1			T23	3		T25	14		T26	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	219555	1			T23	4		T25	14		T26	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	4894936	1			T23	27		T24	69		T25	375
bins_for_gpio_bits[2]	auto[0]	auto[0]	7115956	1			T23	144		T24	52		T25	106
bins_for_gpio_bits[2]	auto[0]	auto[1]	219518	1			T23	10		T25	13		T26	12
bins_for_gpio_bits[2]	auto[1]	auto[0]	219760	1			T23	10		T25	13		T26	13
bins_for_gpio_bits[2]	auto[1]	auto[1]	4897343	1			T23	67		T24	65		T25	372
bins_for_gpio_bits[3]	auto[0]	auto[0]	7123971	1			T23	148		T24	52		T25	108
bins_for_gpio_bits[3]	auto[0]	auto[1]	219333	1			T23	7		T25	8		T26	11
bins_for_gpio_bits[3]	auto[1]	auto[0]	219535	1			T23	7		T25	8		T26	12
bins_for_gpio_bits[3]	auto[1]	auto[1]	4889738	1			T23	69		T24	65		T25	380
bins_for_gpio_bits[4]	auto[0]	auto[0]	7123026	1			T23	185		T24	49		T25	126
bins_for_gpio_bits[4]	auto[0]	auto[1]	219913	1			T23	5		T25	13		T26	11
bins_for_gpio_bits[4]	auto[1]	auto[0]	220141	1			T23	5		T25	13		T26	11
bins_for_gpio_bits[4]	auto[1]	auto[1]	4889497	1			T23	36		T24	68		T25	352
bins_for_gpio_bits[5]	auto[0]	auto[0]	7125450	1			T23	152		T24	46		T25	108
bins_for_gpio_bits[5]	auto[0]	auto[1]	219487	1			T23	8		T25	10		T26	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	219724	1			T23	8		T25	10		T26	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	4887916	1			T23	63		T24	71		T25	376
bins_for_gpio_bits[6]	auto[0]	auto[0]	7119209	1			T23	172		T24	64		T25	99
bins_for_gpio_bits[6]	auto[0]	auto[1]	219410	1			T23	6		T25	10		T26	12
bins_for_gpio_bits[6]	auto[1]	auto[0]	219628	1			T23	7		T25	9		T26	13
bins_for_gpio_bits[6]	auto[1]	auto[1]	4894330	1			T23	46		T24	53		T25	386
bins_for_gpio_bits[7]	auto[0]	auto[0]	7126313	1			T23	173		T24	51		T25	89
bins_for_gpio_bits[7]	auto[0]	auto[1]	219092	1			T23	8		T25	13		T26	11
bins_for_gpio_bits[7]	auto[1]	auto[0]	219325	1			T23	8		T25	12		T26	12
bins_for_gpio_bits[7]	auto[1]	auto[1]	4887847	1			T23	42		T24	66		T25	390
bins_for_gpio_bits[8]	auto[0]	auto[0]	7115685	1			T23	219		T24	56		T25	95
bins_for_gpio_bits[8]	auto[0]	auto[1]	219641	1			T25	9		T26	9		T1	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	219850	1			T23	1		T25	9		T26	10
bins_for_gpio_bits[8]	auto[1]	auto[1]	4897401	1			T23	11		T24	61		T25	391
bins_for_gpio_bits[9]	auto[0]	auto[0]	7114956	1			T23	182		T24	63		T25	77
bins_for_gpio_bits[9]	auto[0]	auto[1]	219757	1			T23	5		T25	9		T26	12
bins_for_gpio_bits[9]	auto[1]	auto[0]	220008	1			T23	5		T25	9		T26	12
bins_for_gpio_bits[9]	auto[1]	auto[1]	4897856	1			T23	39		T24	54		T25	409
bins_for_gpio_bits[10]	auto[0]	auto[0]	7130000	1			T23	162		T24	58		T25	103
bins_for_gpio_bits[10]	auto[0]	auto[1]	219798	1			T23	7		T25	9		T26	9
bins_for_gpio_bits[10]	auto[1]	auto[0]	220024	1			T23	8		T25	9		T26	9
bins_for_gpio_bits[10]	auto[1]	auto[1]	4882755	1			T23	54		T24	59		T25	383
bins_for_gpio_bits[11]	auto[0]	auto[0]	7121988	1			T23	177		T24	59		T25	108
bins_for_gpio_bits[11]	auto[0]	auto[1]	219847	1			T23	4		T25	14		T26	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	220065	1			T23	5		T25	14		T26	10
bins_for_gpio_bits[11]	auto[1]	auto[1]	4890677	1			T23	45		T24	58		T25	368
bins_for_gpio_bits[12]	auto[0]	auto[0]	7130351	1			T23	175		T24	68		T25	93
bins_for_gpio_bits[12]	auto[0]	auto[1]	219689	1			T23	4		T25	11		T26	12
bins_for_gpio_bits[12]	auto[1]	auto[0]	219942	1			T23	4		T25	11		T26	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	4882595	1			T23	48		T24	49		T25	389
bins_for_gpio_bits[13]	auto[0]	auto[0]	7123034	1			T23	166		T24	59		T25	96
bins_for_gpio_bits[13]	auto[0]	auto[1]	219451	1			T23	8		T25	15		T26	9
bins_for_gpio_bits[13]	auto[1]	auto[0]	219692	1			T23	8		T25	14		T26	10
bins_for_gpio_bits[13]	auto[1]	auto[1]	4890400	1			T23	49		T24	58		T25	379
bins_for_gpio_bits[14]	auto[0]	auto[0]	7118186	1			T23	188		T24	59		T25	110
bins_for_gpio_bits[14]	auto[0]	auto[1]	220028	1			T23	6		T25	13		T26	9
bins_for_gpio_bits[14]	auto[1]	auto[0]	220263	1			T23	6		T25	12		T26	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	4894100	1			T23	31		T24	58		T25	369
bins_for_gpio_bits[15]	auto[0]	auto[0]	7120885	1			T23	156		T24	59		T25	83
bins_for_gpio_bits[15]	auto[0]	auto[1]	219200	1			T23	6		T25	14		T26	7
bins_for_gpio_bits[15]	auto[1]	auto[0]	219405	1			T23	7		T25	13		T26	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	4893087	1			T23	62		T24	58		T25	394
bins_for_gpio_bits[16]	auto[0]	auto[0]	7135322	1			T23	166		T24	50		T25	108
bins_for_gpio_bits[16]	auto[0]	auto[1]	219666	1			T23	7		T25	13		T26	13
bins_for_gpio_bits[16]	auto[1]	auto[0]	219901	1			T23	7		T25	13		T26	14
bins_for_gpio_bits[16]	auto[1]	auto[1]	4877688	1			T23	51		T24	67		T25	370
bins_for_gpio_bits[17]	auto[0]	auto[0]	7123097	1			T23	178		T24	47		T25	87
bins_for_gpio_bits[17]	auto[0]	auto[1]	220251	1			T23	7		T25	8		T26	14
bins_for_gpio_bits[17]	auto[1]	auto[0]	220496	1			T23	7		T25	7		T26	14
bins_for_gpio_bits[17]	auto[1]	auto[1]	4888733	1			T23	39		T24	70		T25	402
bins_for_gpio_bits[18]	auto[0]	auto[0]	7129222	1			T23	175		T24	51		T25	99
bins_for_gpio_bits[18]	auto[0]	auto[1]	220238	1			T23	8		T25	14		T26	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	220442	1			T23	8		T25	14		T26	10
bins_for_gpio_bits[18]	auto[1]	auto[1]	4882675	1			T23	40		T24	66		T25	377
bins_for_gpio_bits[19]	auto[0]	auto[0]	7132966	1			T23	199		T24	61		T25	111
bins_for_gpio_bits[19]	auto[0]	auto[1]	219202	1			T23	4		T25	16		T26	12
bins_for_gpio_bits[19]	auto[1]	auto[0]	219421	1			T23	4		T25	16		T26	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	4880988	1			T23	24		T24	56		T25	361
bins_for_gpio_bits[20]	auto[0]	auto[0]	7118234	1			T23	199		T24	57		T25	80
bins_for_gpio_bits[20]	auto[0]	auto[1]	220059	1			T23	5		T25	8		T26	11
bins_for_gpio_bits[20]	auto[1]	auto[0]	220247	1			T23	5		T25	8		T26	11
bins_for_gpio_bits[20]	auto[1]	auto[1]	4894037	1			T23	22		T24	60		T25	408
bins_for_gpio_bits[21]	auto[0]	auto[0]	7125368	1			T23	170		T24	50		T25	97
bins_for_gpio_bits[21]	auto[0]	auto[1]	219924	1			T23	7		T25	11		T26	13
bins_for_gpio_bits[21]	auto[1]	auto[0]	220142	1			T23	7		T25	11		T26	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	4887143	1			T23	47		T24	67		T25	385
bins_for_gpio_bits[22]	auto[0]	auto[0]	7115795	1			T23	210		T24	70		T25	102
bins_for_gpio_bits[22]	auto[0]	auto[1]	220066	1			T23	2		T25	10		T26	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	220310	1			T23	2		T25	10		T26	16
bins_for_gpio_bits[22]	auto[1]	auto[1]	4896406	1			T23	17		T24	47		T25	382
bins_for_gpio_bits[23]	auto[0]	auto[0]	7130438	1			T23	163		T24	70		T25	84
bins_for_gpio_bits[23]	auto[0]	auto[1]	220142	1			T23	5		T25	8		T26	10
bins_for_gpio_bits[23]	auto[1]	auto[0]	220381	1			T23	5		T25	8		T26	11
bins_for_gpio_bits[23]	auto[1]	auto[1]	4881616	1			T23	58		T24	47		T25	404
bins_for_gpio_bits[24]	auto[0]	auto[0]	7119178	1			T23	145		T24	59		T25	116
bins_for_gpio_bits[24]	auto[0]	auto[1]	219610	1			T23	10		T25	12		T26	12
bins_for_gpio_bits[24]	auto[1]	auto[0]	219810	1			T23	10		T25	12		T26	12
bins_for_gpio_bits[24]	auto[1]	auto[1]	4893979	1			T23	66		T24	58		T25	364
bins_for_gpio_bits[25]	auto[0]	auto[0]	7127136	1			T23	187		T24	58		T25	134
bins_for_gpio_bits[25]	auto[0]	auto[1]	220028	1			T23	5		T25	17		T26	12
bins_for_gpio_bits[25]	auto[1]	auto[0]	220260	1			T23	5		T25	17		T26	12
bins_for_gpio_bits[25]	auto[1]	auto[1]	4885153	1			T23	34		T24	59		T25	336
bins_for_gpio_bits[26]	auto[0]	auto[0]	7132286	1			T23	161		T24	57		T25	103
bins_for_gpio_bits[26]	auto[0]	auto[1]	219532	1			T23	7		T25	8		T26	8
bins_for_gpio_bits[26]	auto[1]	auto[0]	219810	1			T23	7		T25	8		T26	8
bins_for_gpio_bits[26]	auto[1]	auto[1]	4880949	1			T23	56		T24	60		T25	385
bins_for_gpio_bits[27]	auto[0]	auto[0]	7120043	1			T23	179		T24	52		T25	75
bins_for_gpio_bits[27]	auto[0]	auto[1]	219267	1			T23	5		T25	5		T26	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	219481	1			T23	5		T25	4		T26	12
bins_for_gpio_bits[27]	auto[1]	auto[1]	4893786	1			T23	42		T24	65		T25	420
bins_for_gpio_bits[28]	auto[0]	auto[0]	7129244	1			T23	166		T24	53		T25	119
bins_for_gpio_bits[28]	auto[0]	auto[1]	219678	1			T23	9		T25	15		T26	12
bins_for_gpio_bits[28]	auto[1]	auto[0]	219916	1			T23	9		T25	15		T26	12
bins_for_gpio_bits[28]	auto[1]	auto[1]	4883739	1			T23	47		T24	64		T25	355
bins_for_gpio_bits[29]	auto[0]	auto[0]	7120532	1			T23	186		T24	62		T25	118
bins_for_gpio_bits[29]	auto[0]	auto[1]	219755	1			T23	5		T25	10		T26	13
bins_for_gpio_bits[29]	auto[1]	auto[0]	220026	1			T23	6		T25	9		T26	13
bins_for_gpio_bits[29]	auto[1]	auto[1]	4892264	1			T23	34		T24	55		T25	367
bins_for_gpio_bits[30]	auto[0]	auto[0]	7135034	1			T23	165		T24	64		T25	88
bins_for_gpio_bits[30]	auto[0]	auto[1]	219672	1			T23	6		T25	10		T26	13
bins_for_gpio_bits[30]	auto[1]	auto[0]	219898	1			T23	7		T25	10		T26	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	4877973	1			T23	53		T24	53		T25	396
bins_for_gpio_bits[31]	auto[0]	auto[0]	7119527	1			T23	183		T24	50		T25	80
bins_for_gpio_bits[31]	auto[0]	auto[1]	219813	1			T23	8		T25	7		T26	9
bins_for_gpio_bits[31]	auto[1]	auto[0]	220059	1			T23	8		T25	6		T26	9
bins_for_gpio_bits[31]	auto[1]	auto[1]	4893178	1			T23	32		T24	67		T25	411