Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7361614 |
1 |
|
|
T23 |
123 |
|
T24 |
152 |
|
T25 |
261 |
| auto[1] |
5229765 |
1 |
|
|
T24 |
95 |
|
T1 |
57 |
|
T11 |
183522 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11931398 |
1 |
|
|
T23 |
123 |
|
T24 |
244 |
|
T25 |
261 |
| auto[1] |
659981 |
1 |
|
|
T24 |
3 |
|
T1 |
8 |
|
T11 |
22476 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7400408 |
1 |
|
|
T23 |
123 |
|
T24 |
140 |
|
T25 |
261 |
| auto[1] |
5190971 |
1 |
|
|
T24 |
107 |
|
T1 |
140 |
|
T11 |
179694 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2257089 |
1 |
|
|
T24 |
64 |
|
T1 |
101 |
|
T11 |
78093 |
| auto[1] |
auto[0] |
auto[1] |
328336 |
1 |
|
|
T24 |
2 |
|
T1 |
5 |
|
T11 |
11072 |
| auto[1] |
auto[1] |
auto[0] |
2273901 |
1 |
|
|
T24 |
40 |
|
T1 |
31 |
|
T11 |
79125 |
| auto[1] |
auto[1] |
auto[1] |
331645 |
1 |
|
|
T24 |
1 |
|
T1 |
3 |
|
T11 |
11404 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371966 |
1 |
|
|
T23 |
123 |
|
T24 |
121 |
|
T25 |
261 |
| auto[1] |
5219413 |
1 |
|
|
T24 |
126 |
|
T1 |
108 |
|
T11 |
179047 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11933376 |
1 |
|
|
T23 |
123 |
|
T24 |
239 |
|
T25 |
261 |
| auto[1] |
658003 |
1 |
|
|
T24 |
8 |
|
T1 |
6 |
|
T11 |
23174 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7417234 |
1 |
|
|
T23 |
123 |
|
T24 |
101 |
|
T25 |
261 |
| auto[1] |
5174145 |
1 |
|
|
T24 |
146 |
|
T1 |
87 |
|
T11 |
183965 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2267045 |
1 |
|
|
T24 |
70 |
|
T1 |
42 |
|
T11 |
84472 |
| auto[1] |
auto[0] |
auto[1] |
330502 |
1 |
|
|
T24 |
7 |
|
T1 |
1 |
|
T11 |
12328 |
| auto[1] |
auto[1] |
auto[0] |
2249097 |
1 |
|
|
T24 |
68 |
|
T1 |
39 |
|
T11 |
76319 |
| auto[1] |
auto[1] |
auto[1] |
327501 |
1 |
|
|
T24 |
1 |
|
T1 |
5 |
|
T11 |
10846 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7395615 |
1 |
|
|
T23 |
123 |
|
T24 |
99 |
|
T25 |
261 |
| auto[1] |
5195764 |
1 |
|
|
T24 |
148 |
|
T1 |
115 |
|
T11 |
181933 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11929044 |
1 |
|
|
T23 |
123 |
|
T24 |
240 |
|
T25 |
261 |
| auto[1] |
662335 |
1 |
|
|
T24 |
7 |
|
T1 |
4 |
|
T11 |
23439 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7382293 |
1 |
|
|
T23 |
123 |
|
T24 |
112 |
|
T25 |
261 |
| auto[1] |
5209086 |
1 |
|
|
T24 |
135 |
|
T1 |
129 |
|
T11 |
185538 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2271172 |
1 |
|
|
T24 |
56 |
|
T1 |
77 |
|
T11 |
80059 |
| auto[1] |
auto[0] |
auto[1] |
331496 |
1 |
|
|
T24 |
4 |
|
T1 |
3 |
|
T11 |
11557 |
| auto[1] |
auto[1] |
auto[0] |
2275579 |
1 |
|
|
T24 |
72 |
|
T1 |
48 |
|
T11 |
82040 |
| auto[1] |
auto[1] |
auto[1] |
330839 |
1 |
|
|
T24 |
3 |
|
T1 |
1 |
|
T11 |
11882 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7387451 |
1 |
|
|
T23 |
123 |
|
T24 |
82 |
|
T25 |
261 |
| auto[1] |
5203928 |
1 |
|
|
T24 |
165 |
|
T1 |
64 |
|
T11 |
178802 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11934564 |
1 |
|
|
T23 |
123 |
|
T24 |
242 |
|
T25 |
261 |
| auto[1] |
656815 |
1 |
|
|
T24 |
5 |
|
T1 |
4 |
|
T11 |
22052 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7422248 |
1 |
|
|
T23 |
123 |
|
T24 |
118 |
|
T25 |
261 |
| auto[1] |
5169131 |
1 |
|
|
T24 |
129 |
|
T1 |
145 |
|
T11 |
177838 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2262750 |
1 |
|
|
T24 |
40 |
|
T1 |
120 |
|
T11 |
78710 |
| auto[1] |
auto[0] |
auto[1] |
328819 |
1 |
|
|
T24 |
2 |
|
T1 |
4 |
|
T11 |
11324 |
| auto[1] |
auto[1] |
auto[0] |
2249566 |
1 |
|
|
T24 |
84 |
|
T1 |
21 |
|
T11 |
77076 |
| auto[1] |
auto[1] |
auto[1] |
327996 |
1 |
|
|
T24 |
3 |
|
T11 |
10728 |
|
T15 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7418655 |
1 |
|
|
T23 |
123 |
|
T24 |
77 |
|
T25 |
261 |
| auto[1] |
5172724 |
1 |
|
|
T24 |
170 |
|
T1 |
126 |
|
T11 |
177498 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928447 |
1 |
|
|
T23 |
123 |
|
T24 |
241 |
|
T25 |
261 |
| auto[1] |
662932 |
1 |
|
|
T24 |
6 |
|
T1 |
4 |
|
T11 |
22435 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7378270 |
1 |
|
|
T23 |
123 |
|
T24 |
149 |
|
T25 |
261 |
| auto[1] |
5213109 |
1 |
|
|
T24 |
98 |
|
T1 |
118 |
|
T11 |
179872 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2294850 |
1 |
|
|
T24 |
29 |
|
T1 |
38 |
|
T11 |
81459 |
| auto[1] |
auto[0] |
auto[1] |
335456 |
1 |
|
|
T1 |
1 |
|
T11 |
11733 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2255327 |
1 |
|
|
T24 |
63 |
|
T1 |
76 |
|
T11 |
75978 |
| auto[1] |
auto[1] |
auto[1] |
327476 |
1 |
|
|
T24 |
6 |
|
T1 |
3 |
|
T11 |
10702 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7413714 |
1 |
|
|
T23 |
123 |
|
T24 |
137 |
|
T25 |
261 |
| auto[1] |
5177665 |
1 |
|
|
T24 |
110 |
|
T1 |
78 |
|
T11 |
181020 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11931769 |
1 |
|
|
T23 |
123 |
|
T24 |
240 |
|
T25 |
261 |
| auto[1] |
659610 |
1 |
|
|
T24 |
7 |
|
T1 |
1 |
|
T11 |
21868 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7414243 |
1 |
|
|
T23 |
123 |
|
T24 |
145 |
|
T25 |
261 |
| auto[1] |
5177136 |
1 |
|
|
T24 |
102 |
|
T1 |
111 |
|
T11 |
176596 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2267985 |
1 |
|
|
T24 |
45 |
|
T1 |
95 |
|
T11 |
76622 |
| auto[1] |
auto[0] |
auto[1] |
331064 |
1 |
|
|
T24 |
5 |
|
T1 |
1 |
|
T11 |
10647 |
| auto[1] |
auto[1] |
auto[0] |
2249541 |
1 |
|
|
T24 |
50 |
|
T1 |
15 |
|
T11 |
78106 |
| auto[1] |
auto[1] |
auto[1] |
328546 |
1 |
|
|
T24 |
2 |
|
T11 |
11221 |
|
T16 |
2177 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371857 |
1 |
|
|
T23 |
123 |
|
T24 |
105 |
|
T25 |
261 |
| auto[1] |
5219522 |
1 |
|
|
T24 |
142 |
|
T1 |
117 |
|
T11 |
179521 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11930927 |
1 |
|
|
T23 |
123 |
|
T24 |
241 |
|
T25 |
261 |
| auto[1] |
660452 |
1 |
|
|
T24 |
6 |
|
T1 |
6 |
|
T11 |
23077 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7408946 |
1 |
|
|
T23 |
123 |
|
T24 |
153 |
|
T25 |
261 |
| auto[1] |
5182433 |
1 |
|
|
T24 |
94 |
|
T1 |
72 |
|
T11 |
184721 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2253483 |
1 |
|
|
T24 |
39 |
|
T1 |
18 |
|
T11 |
81461 |
| auto[1] |
auto[0] |
auto[1] |
329203 |
1 |
|
|
T24 |
3 |
|
T1 |
1 |
|
T11 |
11739 |
| auto[1] |
auto[1] |
auto[0] |
2268498 |
1 |
|
|
T24 |
49 |
|
T1 |
48 |
|
T11 |
80183 |
| auto[1] |
auto[1] |
auto[1] |
331249 |
1 |
|
|
T24 |
3 |
|
T1 |
5 |
|
T11 |
11338 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7379467 |
1 |
|
|
T23 |
123 |
|
T24 |
158 |
|
T25 |
261 |
| auto[1] |
5211912 |
1 |
|
|
T24 |
89 |
|
T1 |
97 |
|
T11 |
185850 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928439 |
1 |
|
|
T23 |
123 |
|
T24 |
241 |
|
T25 |
261 |
| auto[1] |
662940 |
1 |
|
|
T24 |
6 |
|
T1 |
3 |
|
T11 |
21860 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7382370 |
1 |
|
|
T23 |
123 |
|
T24 |
138 |
|
T25 |
261 |
| auto[1] |
5209009 |
1 |
|
|
T24 |
109 |
|
T1 |
115 |
|
T11 |
175984 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2270340 |
1 |
|
|
T24 |
51 |
|
T1 |
81 |
|
T11 |
79124 |
| auto[1] |
auto[0] |
auto[1] |
330594 |
1 |
|
|
T24 |
2 |
|
T1 |
1 |
|
T11 |
11389 |
| auto[1] |
auto[1] |
auto[0] |
2275729 |
1 |
|
|
T24 |
52 |
|
T1 |
31 |
|
T11 |
75000 |
| auto[1] |
auto[1] |
auto[1] |
332346 |
1 |
|
|
T24 |
4 |
|
T1 |
2 |
|
T11 |
10471 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371043 |
1 |
|
|
T23 |
123 |
|
T24 |
153 |
|
T25 |
261 |
| auto[1] |
5220336 |
1 |
|
|
T24 |
94 |
|
T1 |
89 |
|
T11 |
190284 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11930562 |
1 |
|
|
T23 |
123 |
|
T24 |
240 |
|
T25 |
261 |
| auto[1] |
660817 |
1 |
|
|
T24 |
7 |
|
T1 |
3 |
|
T11 |
22343 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7394437 |
1 |
|
|
T23 |
123 |
|
T24 |
105 |
|
T25 |
261 |
| auto[1] |
5196942 |
1 |
|
|
T24 |
142 |
|
T1 |
50 |
|
T11 |
178706 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2280007 |
1 |
|
|
T24 |
77 |
|
T1 |
12 |
|
T11 |
76129 |
| auto[1] |
auto[0] |
auto[1] |
332166 |
1 |
|
|
T24 |
1 |
|
T1 |
2 |
|
T11 |
10823 |
| auto[1] |
auto[1] |
auto[0] |
2256118 |
1 |
|
|
T24 |
58 |
|
T1 |
35 |
|
T11 |
80234 |
| auto[1] |
auto[1] |
auto[1] |
328651 |
1 |
|
|
T24 |
6 |
|
T1 |
1 |
|
T11 |
11520 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7381784 |
1 |
|
|
T23 |
123 |
|
T24 |
111 |
|
T25 |
261 |
| auto[1] |
5209595 |
1 |
|
|
T24 |
136 |
|
T1 |
43 |
|
T11 |
178867 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11926435 |
1 |
|
|
T23 |
123 |
|
T24 |
239 |
|
T25 |
261 |
| auto[1] |
664944 |
1 |
|
|
T24 |
8 |
|
T1 |
5 |
|
T11 |
22993 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371840 |
1 |
|
|
T23 |
123 |
|
T24 |
157 |
|
T25 |
261 |
| auto[1] |
5219539 |
1 |
|
|
T24 |
90 |
|
T1 |
111 |
|
T11 |
183933 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2272338 |
1 |
|
|
T24 |
30 |
|
T1 |
81 |
|
T11 |
84574 |
| auto[1] |
auto[0] |
auto[1] |
330404 |
1 |
|
|
T24 |
2 |
|
T1 |
4 |
|
T11 |
12134 |
| auto[1] |
auto[1] |
auto[0] |
2282257 |
1 |
|
|
T24 |
52 |
|
T1 |
25 |
|
T11 |
76366 |
| auto[1] |
auto[1] |
auto[1] |
334540 |
1 |
|
|
T24 |
6 |
|
T1 |
1 |
|
T11 |
10859 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7355666 |
1 |
|
|
T23 |
123 |
|
T24 |
108 |
|
T25 |
261 |
| auto[1] |
5235713 |
1 |
|
|
T24 |
139 |
|
T1 |
61 |
|
T11 |
185725 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11925684 |
1 |
|
|
T23 |
123 |
|
T24 |
241 |
|
T25 |
261 |
| auto[1] |
665695 |
1 |
|
|
T24 |
6 |
|
T1 |
5 |
|
T11 |
22212 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7361742 |
1 |
|
|
T23 |
123 |
|
T24 |
129 |
|
T25 |
261 |
| auto[1] |
5229637 |
1 |
|
|
T24 |
118 |
|
T1 |
135 |
|
T11 |
179027 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2280259 |
1 |
|
|
T24 |
34 |
|
T1 |
98 |
|
T11 |
78414 |
| auto[1] |
auto[0] |
auto[1] |
332558 |
1 |
|
|
T24 |
3 |
|
T1 |
4 |
|
T11 |
11203 |
| auto[1] |
auto[1] |
auto[0] |
2283683 |
1 |
|
|
T24 |
78 |
|
T1 |
32 |
|
T11 |
78401 |
| auto[1] |
auto[1] |
auto[1] |
333137 |
1 |
|
|
T24 |
3 |
|
T1 |
1 |
|
T11 |
11009 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7359424 |
1 |
|
|
T23 |
123 |
|
T24 |
74 |
|
T25 |
261 |
| auto[1] |
5231955 |
1 |
|
|
T24 |
173 |
|
T1 |
95 |
|
T11 |
187923 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11930705 |
1 |
|
|
T23 |
123 |
|
T24 |
241 |
|
T25 |
261 |
| auto[1] |
660674 |
1 |
|
|
T24 |
6 |
|
T1 |
5 |
|
T11 |
23219 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7395643 |
1 |
|
|
T23 |
123 |
|
T24 |
114 |
|
T25 |
261 |
| auto[1] |
5195736 |
1 |
|
|
T24 |
133 |
|
T1 |
136 |
|
T11 |
186007 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2247753 |
1 |
|
|
T24 |
59 |
|
T1 |
66 |
|
T11 |
76437 |
| auto[1] |
auto[0] |
auto[1] |
326960 |
1 |
|
|
T24 |
3 |
|
T1 |
3 |
|
T11 |
10642 |
| auto[1] |
auto[1] |
auto[0] |
2287309 |
1 |
|
|
T24 |
68 |
|
T1 |
65 |
|
T11 |
86351 |
| auto[1] |
auto[1] |
auto[1] |
333714 |
1 |
|
|
T24 |
3 |
|
T1 |
2 |
|
T11 |
12577 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7378799 |
1 |
|
|
T23 |
123 |
|
T24 |
162 |
|
T25 |
261 |
| auto[1] |
5212580 |
1 |
|
|
T24 |
85 |
|
T1 |
125 |
|
T11 |
185096 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11929766 |
1 |
|
|
T23 |
123 |
|
T24 |
244 |
|
T25 |
261 |
| auto[1] |
661613 |
1 |
|
|
T24 |
3 |
|
T1 |
3 |
|
T11 |
22178 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7388563 |
1 |
|
|
T23 |
123 |
|
T24 |
177 |
|
T25 |
261 |
| auto[1] |
5202816 |
1 |
|
|
T24 |
70 |
|
T1 |
85 |
|
T11 |
179294 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2263219 |
1 |
|
|
T24 |
51 |
|
T1 |
38 |
|
T11 |
76848 |
| auto[1] |
auto[0] |
auto[1] |
329758 |
1 |
|
|
T24 |
2 |
|
T1 |
1 |
|
T11 |
10793 |
| auto[1] |
auto[1] |
auto[0] |
2277984 |
1 |
|
|
T24 |
16 |
|
T1 |
44 |
|
T11 |
80268 |
| auto[1] |
auto[1] |
auto[1] |
331855 |
1 |
|
|
T24 |
1 |
|
T1 |
2 |
|
T11 |
11385 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7407810 |
1 |
|
|
T23 |
123 |
|
T24 |
125 |
|
T25 |
261 |
| auto[1] |
5183569 |
1 |
|
|
T24 |
122 |
|
T1 |
121 |
|
T11 |
182244 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11931495 |
1 |
|
|
T23 |
123 |
|
T24 |
236 |
|
T25 |
261 |
| auto[1] |
659884 |
1 |
|
|
T24 |
11 |
|
T1 |
6 |
|
T11 |
22894 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7398874 |
1 |
|
|
T23 |
123 |
|
T24 |
64 |
|
T25 |
261 |
| auto[1] |
5192505 |
1 |
|
|
T24 |
183 |
|
T1 |
120 |
|
T11 |
184084 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2286406 |
1 |
|
|
T24 |
78 |
|
T1 |
44 |
|
T11 |
79785 |
| auto[1] |
auto[0] |
auto[1] |
333490 |
1 |
|
|
T24 |
6 |
|
T1 |
2 |
|
T11 |
11307 |
| auto[1] |
auto[1] |
auto[0] |
2246215 |
1 |
|
|
T24 |
94 |
|
T1 |
70 |
|
T11 |
81405 |
| auto[1] |
auto[1] |
auto[1] |
326394 |
1 |
|
|
T24 |
5 |
|
T1 |
4 |
|
T11 |
11587 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7390914 |
1 |
|
|
T23 |
123 |
|
T24 |
130 |
|
T25 |
261 |
| auto[1] |
5200465 |
1 |
|
|
T24 |
117 |
|
T1 |
81 |
|
T11 |
182004 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11931428 |
1 |
|
|
T23 |
123 |
|
T24 |
238 |
|
T25 |
261 |
| auto[1] |
659951 |
1 |
|
|
T24 |
9 |
|
T1 |
1 |
|
T11 |
22107 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7394122 |
1 |
|
|
T23 |
123 |
|
T24 |
116 |
|
T25 |
261 |
| auto[1] |
5197257 |
1 |
|
|
T24 |
131 |
|
T1 |
54 |
|
T11 |
178900 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2278388 |
1 |
|
|
T24 |
76 |
|
T1 |
29 |
|
T11 |
76824 |
| auto[1] |
auto[0] |
auto[1] |
332293 |
1 |
|
|
T24 |
2 |
|
T1 |
1 |
|
T11 |
10864 |
| auto[1] |
auto[1] |
auto[0] |
2258918 |
1 |
|
|
T24 |
46 |
|
T1 |
24 |
|
T11 |
79969 |
| auto[1] |
auto[1] |
auto[1] |
327658 |
1 |
|
|
T24 |
7 |
|
T11 |
11243 |
|
T16 |
2180 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7402783 |
1 |
|
|
T23 |
123 |
|
T24 |
121 |
|
T25 |
261 |
| auto[1] |
5188596 |
1 |
|
|
T24 |
126 |
|
T1 |
153 |
|
T11 |
185796 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928366 |
1 |
|
|
T23 |
123 |
|
T24 |
242 |
|
T25 |
261 |
| auto[1] |
663013 |
1 |
|
|
T24 |
5 |
|
T11 |
22467 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7375711 |
1 |
|
|
T23 |
123 |
|
T24 |
150 |
|
T25 |
261 |
| auto[1] |
5215668 |
1 |
|
|
T24 |
97 |
|
T1 |
73 |
|
T11 |
178687 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2276253 |
1 |
|
|
T24 |
30 |
|
T1 |
24 |
|
T11 |
79986 |
| auto[1] |
auto[0] |
auto[1] |
331757 |
1 |
|
|
T11 |
11375 |
|
T16 |
2015 |
|
T17 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2276402 |
1 |
|
|
T24 |
62 |
|
T1 |
49 |
|
T11 |
76234 |
| auto[1] |
auto[1] |
auto[1] |
331256 |
1 |
|
|
T24 |
5 |
|
T11 |
11092 |
|
T15 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7363869 |
1 |
|
|
T23 |
123 |
|
T24 |
134 |
|
T25 |
261 |
| auto[1] |
5227510 |
1 |
|
|
T24 |
113 |
|
T1 |
169 |
|
T11 |
179436 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11929735 |
1 |
|
|
T23 |
123 |
|
T24 |
238 |
|
T25 |
261 |
| auto[1] |
661644 |
1 |
|
|
T24 |
9 |
|
T1 |
2 |
|
T11 |
23120 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7392544 |
1 |
|
|
T23 |
123 |
|
T24 |
111 |
|
T25 |
261 |
| auto[1] |
5198835 |
1 |
|
|
T24 |
136 |
|
T1 |
87 |
|
T11 |
184427 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2264986 |
1 |
|
|
T24 |
59 |
|
T1 |
20 |
|
T11 |
81683 |
| auto[1] |
auto[0] |
auto[1] |
329641 |
1 |
|
|
T24 |
4 |
|
T1 |
2 |
|
T11 |
11841 |
| auto[1] |
auto[1] |
auto[0] |
2272205 |
1 |
|
|
T24 |
68 |
|
T1 |
65 |
|
T11 |
79624 |
| auto[1] |
auto[1] |
auto[1] |
332003 |
1 |
|
|
T24 |
5 |
|
T11 |
11279 |
|
T16 |
2202 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7364140 |
1 |
|
|
T23 |
123 |
|
T24 |
132 |
|
T25 |
261 |
| auto[1] |
5227239 |
1 |
|
|
T24 |
115 |
|
T1 |
52 |
|
T11 |
182337 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11925626 |
1 |
|
|
T23 |
123 |
|
T24 |
239 |
|
T25 |
261 |
| auto[1] |
665753 |
1 |
|
|
T24 |
8 |
|
T1 |
6 |
|
T11 |
23775 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7372067 |
1 |
|
|
T23 |
123 |
|
T24 |
152 |
|
T25 |
261 |
| auto[1] |
5219312 |
1 |
|
|
T24 |
95 |
|
T1 |
140 |
|
T11 |
186314 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2269246 |
1 |
|
|
T24 |
42 |
|
T1 |
85 |
|
T11 |
79602 |
| auto[1] |
auto[0] |
auto[1] |
330993 |
1 |
|
|
T24 |
5 |
|
T1 |
3 |
|
T11 |
11606 |
| auto[1] |
auto[1] |
auto[0] |
2284313 |
1 |
|
|
T24 |
45 |
|
T1 |
49 |
|
T11 |
82937 |
| auto[1] |
auto[1] |
auto[1] |
334760 |
1 |
|
|
T24 |
3 |
|
T1 |
3 |
|
T11 |
12169 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7387951 |
1 |
|
|
T23 |
123 |
|
T24 |
143 |
|
T25 |
261 |
| auto[1] |
5203428 |
1 |
|
|
T24 |
104 |
|
T1 |
74 |
|
T11 |
182329 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11924889 |
1 |
|
|
T23 |
123 |
|
T24 |
240 |
|
T25 |
261 |
| auto[1] |
666490 |
1 |
|
|
T24 |
7 |
|
T1 |
7 |
|
T11 |
22315 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7363966 |
1 |
|
|
T23 |
123 |
|
T24 |
93 |
|
T25 |
261 |
| auto[1] |
5227413 |
1 |
|
|
T24 |
154 |
|
T1 |
120 |
|
T11 |
180253 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2293403 |
1 |
|
|
T24 |
91 |
|
T1 |
70 |
|
T11 |
84055 |
| auto[1] |
auto[0] |
auto[1] |
336289 |
1 |
|
|
T24 |
4 |
|
T1 |
6 |
|
T11 |
12119 |
| auto[1] |
auto[1] |
auto[0] |
2267520 |
1 |
|
|
T24 |
56 |
|
T1 |
43 |
|
T11 |
73883 |
| auto[1] |
auto[1] |
auto[1] |
330201 |
1 |
|
|
T24 |
3 |
|
T1 |
1 |
|
T11 |
10196 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |