Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7353315 |
1 |
|
|
T23 |
123 |
|
T24 |
114 |
|
T25 |
261 |
| auto[1] |
5238064 |
1 |
|
|
T24 |
133 |
|
T1 |
51 |
|
T11 |
190687 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11927509 |
1 |
|
|
T23 |
123 |
|
T24 |
241 |
|
T25 |
261 |
| auto[1] |
663870 |
1 |
|
|
T24 |
6 |
|
T1 |
5 |
|
T11 |
22046 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7374223 |
1 |
|
|
T23 |
123 |
|
T24 |
130 |
|
T25 |
261 |
| auto[1] |
5217156 |
1 |
|
|
T24 |
117 |
|
T1 |
119 |
|
T11 |
175789 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2259053 |
1 |
|
|
T24 |
41 |
|
T1 |
83 |
|
T11 |
74380 |
| auto[1] |
auto[0] |
auto[1] |
327871 |
1 |
|
|
T24 |
3 |
|
T1 |
1 |
|
T11 |
10430 |
| auto[1] |
auto[1] |
auto[0] |
2294233 |
1 |
|
|
T24 |
70 |
|
T1 |
31 |
|
T11 |
79363 |
| auto[1] |
auto[1] |
auto[1] |
335999 |
1 |
|
|
T24 |
3 |
|
T1 |
4 |
|
T11 |
11616 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |