Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7388063 |
1 |
|
|
T23 |
123 |
|
T24 |
112 |
|
T25 |
261 |
| auto[1] |
5203316 |
1 |
|
|
T24 |
135 |
|
T1 |
78 |
|
T11 |
183940 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11925445 |
1 |
|
|
T23 |
123 |
|
T24 |
238 |
|
T25 |
261 |
| auto[1] |
665934 |
1 |
|
|
T24 |
9 |
|
T1 |
4 |
|
T11 |
22567 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7362695 |
1 |
|
|
T23 |
123 |
|
T24 |
112 |
|
T25 |
261 |
| auto[1] |
5228684 |
1 |
|
|
T24 |
135 |
|
T1 |
75 |
|
T11 |
181240 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2284193 |
1 |
|
|
T24 |
63 |
|
T1 |
44 |
|
T11 |
79563 |
| auto[1] |
auto[0] |
auto[1] |
332481 |
1 |
|
|
T24 |
4 |
|
T1 |
3 |
|
T11 |
11490 |
| auto[1] |
auto[1] |
auto[0] |
2278557 |
1 |
|
|
T24 |
63 |
|
T1 |
27 |
|
T11 |
79110 |
| auto[1] |
auto[1] |
auto[1] |
333453 |
1 |
|
|
T24 |
5 |
|
T1 |
1 |
|
T11 |
11077 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |