Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7378148 |
1 |
|
|
T23 |
123 |
|
T24 |
124 |
|
T25 |
261 |
| auto[1] |
5213231 |
1 |
|
|
T24 |
123 |
|
T1 |
44 |
|
T11 |
184999 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11926695 |
1 |
|
|
T23 |
123 |
|
T24 |
239 |
|
T25 |
261 |
| auto[1] |
664684 |
1 |
|
|
T24 |
8 |
|
T1 |
2 |
|
T11 |
24539 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7369985 |
1 |
|
|
T23 |
123 |
|
T24 |
134 |
|
T25 |
261 |
| auto[1] |
5221394 |
1 |
|
|
T24 |
113 |
|
T1 |
90 |
|
T11 |
191176 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2274205 |
1 |
|
|
T24 |
45 |
|
T1 |
67 |
|
T11 |
82600 |
| auto[1] |
auto[0] |
auto[1] |
332346 |
1 |
|
|
T24 |
4 |
|
T1 |
2 |
|
T11 |
12208 |
| auto[1] |
auto[1] |
auto[0] |
2282505 |
1 |
|
|
T24 |
60 |
|
T1 |
21 |
|
T11 |
84037 |
| auto[1] |
auto[1] |
auto[1] |
332338 |
1 |
|
|
T24 |
4 |
|
T11 |
12331 |
|
T15 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |