Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7390752 |
1 |
|
|
T23 |
123 |
|
T24 |
125 |
|
T25 |
261 |
| auto[1] |
5200627 |
1 |
|
|
T24 |
122 |
|
T1 |
146 |
|
T11 |
183261 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928392 |
1 |
|
|
T23 |
123 |
|
T24 |
237 |
|
T25 |
261 |
| auto[1] |
662987 |
1 |
|
|
T24 |
10 |
|
T1 |
5 |
|
T11 |
22545 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7383340 |
1 |
|
|
T23 |
123 |
|
T24 |
143 |
|
T25 |
261 |
| auto[1] |
5208039 |
1 |
|
|
T24 |
104 |
|
T1 |
96 |
|
T11 |
180161 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2292335 |
1 |
|
|
T24 |
36 |
|
T1 |
27 |
|
T11 |
79262 |
| auto[1] |
auto[0] |
auto[1] |
335333 |
1 |
|
|
T24 |
4 |
|
T11 |
11351 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2252717 |
1 |
|
|
T24 |
58 |
|
T1 |
64 |
|
T11 |
78354 |
| auto[1] |
auto[1] |
auto[1] |
327654 |
1 |
|
|
T24 |
6 |
|
T1 |
5 |
|
T11 |
11194 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |