Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7358901 |
1 |
|
|
T23 |
123 |
|
T24 |
112 |
|
T25 |
261 |
| auto[1] |
5232478 |
1 |
|
|
T24 |
135 |
|
T1 |
59 |
|
T11 |
185619 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11934533 |
1 |
|
|
T23 |
123 |
|
T24 |
245 |
|
T25 |
261 |
| auto[1] |
656846 |
1 |
|
|
T24 |
2 |
|
T1 |
7 |
|
T11 |
23492 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7412084 |
1 |
|
|
T23 |
123 |
|
T24 |
194 |
|
T25 |
261 |
| auto[1] |
5179295 |
1 |
|
|
T24 |
53 |
|
T1 |
146 |
|
T11 |
185657 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2255445 |
1 |
|
|
T24 |
15 |
|
T1 |
105 |
|
T11 |
80290 |
| auto[1] |
auto[0] |
auto[1] |
326668 |
1 |
|
|
T24 |
1 |
|
T1 |
6 |
|
T11 |
11653 |
| auto[1] |
auto[1] |
auto[0] |
2267004 |
1 |
|
|
T24 |
36 |
|
T1 |
34 |
|
T11 |
81875 |
| auto[1] |
auto[1] |
auto[1] |
330178 |
1 |
|
|
T24 |
1 |
|
T1 |
1 |
|
T11 |
11839 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |