Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7361614 |
1 |
|
|
T23 |
123 |
|
T24 |
152 |
|
T25 |
261 |
| auto[1] |
5229765 |
1 |
|
|
T24 |
95 |
|
T1 |
57 |
|
T11 |
183522 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10429427 |
1 |
|
|
T23 |
123 |
|
T24 |
209 |
|
T25 |
261 |
| auto[1] |
2161952 |
1 |
|
|
T24 |
38 |
|
T1 |
66 |
|
T11 |
65866 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7384668 |
1 |
|
|
T23 |
123 |
|
T24 |
152 |
|
T25 |
261 |
| auto[1] |
5206711 |
1 |
|
|
T24 |
95 |
|
T1 |
88 |
|
T11 |
180635 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1515284 |
1 |
|
|
T24 |
46 |
|
T1 |
16 |
|
T11 |
55933 |
| auto[1] |
auto[0] |
auto[1] |
1079076 |
1 |
|
|
T24 |
23 |
|
T1 |
46 |
|
T11 |
31537 |
| auto[1] |
auto[1] |
auto[0] |
1529475 |
1 |
|
|
T24 |
11 |
|
T1 |
6 |
|
T11 |
58836 |
| auto[1] |
auto[1] |
auto[1] |
1082876 |
1 |
|
|
T24 |
15 |
|
T1 |
20 |
|
T11 |
34329 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |