Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371966 |
1 |
|
|
T23 |
123 |
|
T24 |
121 |
|
T25 |
261 |
| auto[1] |
5219413 |
1 |
|
|
T24 |
126 |
|
T1 |
108 |
|
T11 |
179047 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10410937 |
1 |
|
|
T23 |
123 |
|
T24 |
200 |
|
T25 |
261 |
| auto[1] |
2180442 |
1 |
|
|
T24 |
47 |
|
T1 |
117 |
|
T11 |
68320 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7367508 |
1 |
|
|
T23 |
123 |
|
T24 |
157 |
|
T25 |
261 |
| auto[1] |
5223871 |
1 |
|
|
T24 |
90 |
|
T1 |
135 |
|
T11 |
185068 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1516541 |
1 |
|
|
T24 |
20 |
|
T1 |
2 |
|
T11 |
59315 |
| auto[1] |
auto[0] |
auto[1] |
1086811 |
1 |
|
|
T24 |
27 |
|
T1 |
41 |
|
T11 |
34274 |
| auto[1] |
auto[1] |
auto[0] |
1526888 |
1 |
|
|
T24 |
23 |
|
T1 |
16 |
|
T11 |
57433 |
| auto[1] |
auto[1] |
auto[1] |
1093631 |
1 |
|
|
T24 |
20 |
|
T1 |
76 |
|
T11 |
34046 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |