Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7395615 |
1 |
|
|
T23 |
123 |
|
T24 |
99 |
|
T25 |
261 |
| auto[1] |
5195764 |
1 |
|
|
T24 |
148 |
|
T1 |
115 |
|
T11 |
181933 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10422102 |
1 |
|
|
T23 |
123 |
|
T24 |
223 |
|
T25 |
261 |
| auto[1] |
2169277 |
1 |
|
|
T24 |
24 |
|
T1 |
94 |
|
T11 |
66957 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7393288 |
1 |
|
|
T23 |
123 |
|
T24 |
170 |
|
T25 |
261 |
| auto[1] |
5198091 |
1 |
|
|
T24 |
77 |
|
T1 |
105 |
|
T11 |
178641 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1513809 |
1 |
|
|
T24 |
3 |
|
T11 |
55564 |
|
T15 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1087114 |
1 |
|
|
T24 |
2 |
|
T1 |
29 |
|
T11 |
32925 |
| auto[1] |
auto[1] |
auto[0] |
1515005 |
1 |
|
|
T24 |
50 |
|
T1 |
11 |
|
T11 |
56120 |
| auto[1] |
auto[1] |
auto[1] |
1082163 |
1 |
|
|
T24 |
22 |
|
T1 |
65 |
|
T11 |
34032 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |