Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7387451 |
1 |
|
|
T23 |
123 |
|
T24 |
82 |
|
T25 |
261 |
| auto[1] |
5203928 |
1 |
|
|
T24 |
165 |
|
T1 |
64 |
|
T11 |
178802 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10422956 |
1 |
|
|
T23 |
123 |
|
T24 |
193 |
|
T25 |
261 |
| auto[1] |
2168423 |
1 |
|
|
T24 |
54 |
|
T1 |
87 |
|
T11 |
67095 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7384309 |
1 |
|
|
T23 |
123 |
|
T24 |
148 |
|
T25 |
261 |
| auto[1] |
5207070 |
1 |
|
|
T24 |
99 |
|
T1 |
108 |
|
T11 |
181861 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1520016 |
1 |
|
|
T24 |
6 |
|
T1 |
20 |
|
T11 |
58648 |
| auto[1] |
auto[0] |
auto[1] |
1085336 |
1 |
|
|
T24 |
11 |
|
T1 |
65 |
|
T11 |
34037 |
| auto[1] |
auto[1] |
auto[0] |
1518631 |
1 |
|
|
T24 |
39 |
|
T1 |
1 |
|
T11 |
56118 |
| auto[1] |
auto[1] |
auto[1] |
1083087 |
1 |
|
|
T24 |
43 |
|
T1 |
22 |
|
T11 |
33058 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |