Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7418655 |
1 |
|
|
T23 |
123 |
|
T24 |
77 |
|
T25 |
261 |
| auto[1] |
5172724 |
1 |
|
|
T24 |
170 |
|
T1 |
126 |
|
T11 |
177498 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10418334 |
1 |
|
|
T23 |
123 |
|
T24 |
175 |
|
T25 |
261 |
| auto[1] |
2173045 |
1 |
|
|
T24 |
72 |
|
T1 |
66 |
|
T11 |
67259 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7377414 |
1 |
|
|
T23 |
123 |
|
T24 |
78 |
|
T25 |
261 |
| auto[1] |
5213965 |
1 |
|
|
T24 |
169 |
|
T1 |
86 |
|
T11 |
180830 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1536067 |
1 |
|
|
T24 |
25 |
|
T1 |
2 |
|
T11 |
57707 |
| auto[1] |
auto[0] |
auto[1] |
1096970 |
1 |
|
|
T24 |
20 |
|
T1 |
21 |
|
T11 |
33927 |
| auto[1] |
auto[1] |
auto[0] |
1504853 |
1 |
|
|
T24 |
72 |
|
T1 |
18 |
|
T11 |
55864 |
| auto[1] |
auto[1] |
auto[1] |
1076075 |
1 |
|
|
T24 |
52 |
|
T1 |
45 |
|
T11 |
33332 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |