Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7376090 |
1 |
|
|
T23 |
123 |
|
T24 |
123 |
|
T25 |
261 |
| auto[1] |
5215289 |
1 |
|
|
T24 |
124 |
|
T1 |
54 |
|
T11 |
176644 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928925 |
1 |
|
|
T23 |
123 |
|
T24 |
238 |
|
T25 |
261 |
| auto[1] |
662454 |
1 |
|
|
T24 |
9 |
|
T1 |
5 |
|
T11 |
23157 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7380125 |
1 |
|
|
T23 |
123 |
|
T24 |
127 |
|
T25 |
261 |
| auto[1] |
5211254 |
1 |
|
|
T24 |
120 |
|
T1 |
128 |
|
T11 |
184476 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2273089 |
1 |
|
|
T24 |
66 |
|
T1 |
89 |
|
T11 |
81765 |
| auto[1] |
auto[0] |
auto[1] |
330731 |
1 |
|
|
T24 |
6 |
|
T1 |
3 |
|
T11 |
11728 |
| auto[1] |
auto[1] |
auto[0] |
2275711 |
1 |
|
|
T24 |
45 |
|
T1 |
34 |
|
T11 |
79554 |
| auto[1] |
auto[1] |
auto[1] |
331723 |
1 |
|
|
T24 |
3 |
|
T1 |
2 |
|
T11 |
11429 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |