Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7413714 |
1 |
|
|
T23 |
123 |
|
T24 |
137 |
|
T25 |
261 |
| auto[1] |
5177665 |
1 |
|
|
T24 |
110 |
|
T1 |
78 |
|
T11 |
181020 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10421931 |
1 |
|
|
T23 |
123 |
|
T24 |
172 |
|
T25 |
261 |
| auto[1] |
2169448 |
1 |
|
|
T24 |
75 |
|
T1 |
115 |
|
T11 |
66743 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7381517 |
1 |
|
|
T23 |
123 |
|
T24 |
107 |
|
T25 |
261 |
| auto[1] |
5209862 |
1 |
|
|
T24 |
140 |
|
T1 |
127 |
|
T11 |
180505 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1530909 |
1 |
|
|
T24 |
30 |
|
T1 |
12 |
|
T11 |
57096 |
| auto[1] |
auto[0] |
auto[1] |
1089338 |
1 |
|
|
T24 |
43 |
|
T1 |
63 |
|
T11 |
33306 |
| auto[1] |
auto[1] |
auto[0] |
1509505 |
1 |
|
|
T24 |
35 |
|
T11 |
56666 |
|
T16 |
7383 |
| auto[1] |
auto[1] |
auto[1] |
1080110 |
1 |
|
|
T24 |
32 |
|
T1 |
52 |
|
T11 |
33437 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |