Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371857 |
1 |
|
|
T23 |
123 |
|
T24 |
105 |
|
T25 |
261 |
| auto[1] |
5219522 |
1 |
|
|
T24 |
142 |
|
T1 |
117 |
|
T11 |
179521 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10428185 |
1 |
|
|
T23 |
123 |
|
T24 |
186 |
|
T25 |
261 |
| auto[1] |
2163194 |
1 |
|
|
T24 |
61 |
|
T1 |
80 |
|
T11 |
69418 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7396125 |
1 |
|
|
T23 |
123 |
|
T24 |
133 |
|
T25 |
261 |
| auto[1] |
5195254 |
1 |
|
|
T24 |
114 |
|
T1 |
88 |
|
T11 |
187163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1509618 |
1 |
|
|
T24 |
26 |
|
T1 |
7 |
|
T11 |
60786 |
| auto[1] |
auto[0] |
auto[1] |
1087739 |
1 |
|
|
T24 |
26 |
|
T1 |
41 |
|
T11 |
35872 |
| auto[1] |
auto[1] |
auto[0] |
1522442 |
1 |
|
|
T24 |
27 |
|
T1 |
1 |
|
T11 |
56959 |
| auto[1] |
auto[1] |
auto[1] |
1075455 |
1 |
|
|
T24 |
35 |
|
T1 |
39 |
|
T11 |
33546 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |