Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7379467 |
1 |
|
|
T23 |
123 |
|
T24 |
158 |
|
T25 |
261 |
| auto[1] |
5211912 |
1 |
|
|
T24 |
89 |
|
T1 |
97 |
|
T11 |
185850 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10416607 |
1 |
|
|
T23 |
123 |
|
T24 |
204 |
|
T25 |
261 |
| auto[1] |
2174772 |
1 |
|
|
T24 |
43 |
|
T1 |
86 |
|
T11 |
68468 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7380713 |
1 |
|
|
T23 |
123 |
|
T24 |
146 |
|
T25 |
261 |
| auto[1] |
5210666 |
1 |
|
|
T24 |
101 |
|
T1 |
129 |
|
T11 |
182125 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1521297 |
1 |
|
|
T24 |
44 |
|
T1 |
5 |
|
T11 |
56531 |
| auto[1] |
auto[0] |
auto[1] |
1088239 |
1 |
|
|
T24 |
34 |
|
T1 |
39 |
|
T11 |
34166 |
| auto[1] |
auto[1] |
auto[0] |
1514597 |
1 |
|
|
T24 |
14 |
|
T1 |
38 |
|
T11 |
57126 |
| auto[1] |
auto[1] |
auto[1] |
1086533 |
1 |
|
|
T24 |
9 |
|
T1 |
47 |
|
T11 |
34302 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |