Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371043 |
1 |
|
|
T23 |
123 |
|
T24 |
153 |
|
T25 |
261 |
| auto[1] |
5220336 |
1 |
|
|
T24 |
94 |
|
T1 |
89 |
|
T11 |
190284 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10417081 |
1 |
|
|
T23 |
123 |
|
T24 |
152 |
|
T25 |
261 |
| auto[1] |
2174298 |
1 |
|
|
T24 |
95 |
|
T1 |
107 |
|
T11 |
66730 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7363623 |
1 |
|
|
T23 |
123 |
|
T24 |
117 |
|
T25 |
261 |
| auto[1] |
5227756 |
1 |
|
|
T24 |
130 |
|
T1 |
129 |
|
T11 |
179660 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1533896 |
1 |
|
|
T24 |
12 |
|
T1 |
16 |
|
T11 |
53694 |
| auto[1] |
auto[0] |
auto[1] |
1091995 |
1 |
|
|
T24 |
56 |
|
T1 |
58 |
|
T11 |
32224 |
| auto[1] |
auto[1] |
auto[0] |
1519562 |
1 |
|
|
T24 |
23 |
|
T1 |
6 |
|
T11 |
59236 |
| auto[1] |
auto[1] |
auto[1] |
1082303 |
1 |
|
|
T24 |
39 |
|
T1 |
49 |
|
T11 |
34506 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |