Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7381784 |
1 |
|
|
T23 |
123 |
|
T24 |
111 |
|
T25 |
261 |
| auto[1] |
5209595 |
1 |
|
|
T24 |
136 |
|
T1 |
43 |
|
T11 |
178867 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10422637 |
1 |
|
|
T23 |
123 |
|
T24 |
140 |
|
T25 |
261 |
| auto[1] |
2168742 |
1 |
|
|
T24 |
107 |
|
T1 |
74 |
|
T11 |
66967 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7386905 |
1 |
|
|
T23 |
123 |
|
T24 |
69 |
|
T25 |
261 |
| auto[1] |
5204474 |
1 |
|
|
T24 |
178 |
|
T1 |
107 |
|
T11 |
179938 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1518467 |
1 |
|
|
T24 |
36 |
|
T1 |
29 |
|
T11 |
55751 |
| auto[1] |
auto[0] |
auto[1] |
1084248 |
1 |
|
|
T24 |
50 |
|
T1 |
68 |
|
T11 |
32896 |
| auto[1] |
auto[1] |
auto[0] |
1517265 |
1 |
|
|
T24 |
35 |
|
T1 |
4 |
|
T11 |
57220 |
| auto[1] |
auto[1] |
auto[1] |
1084494 |
1 |
|
|
T24 |
57 |
|
T1 |
6 |
|
T11 |
34071 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |