Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7355666 |
1 |
|
|
T23 |
123 |
|
T24 |
108 |
|
T25 |
261 |
| auto[1] |
5235713 |
1 |
|
|
T24 |
139 |
|
T1 |
61 |
|
T11 |
185725 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10420407 |
1 |
|
|
T23 |
123 |
|
T24 |
197 |
|
T25 |
261 |
| auto[1] |
2170972 |
1 |
|
|
T24 |
50 |
|
T1 |
93 |
|
T11 |
66760 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7381341 |
1 |
|
|
T23 |
123 |
|
T24 |
146 |
|
T25 |
261 |
| auto[1] |
5210038 |
1 |
|
|
T24 |
101 |
|
T1 |
105 |
|
T11 |
181329 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1514378 |
1 |
|
|
T24 |
19 |
|
T1 |
8 |
|
T11 |
55700 |
| auto[1] |
auto[0] |
auto[1] |
1081094 |
1 |
|
|
T24 |
21 |
|
T1 |
73 |
|
T11 |
33177 |
| auto[1] |
auto[1] |
auto[0] |
1524688 |
1 |
|
|
T24 |
32 |
|
T1 |
4 |
|
T11 |
58869 |
| auto[1] |
auto[1] |
auto[1] |
1089878 |
1 |
|
|
T24 |
29 |
|
T1 |
20 |
|
T11 |
33583 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |