Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7359424 |
1 |
|
|
T23 |
123 |
|
T24 |
74 |
|
T25 |
261 |
| auto[1] |
5231955 |
1 |
|
|
T24 |
173 |
|
T1 |
95 |
|
T11 |
187923 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10415794 |
1 |
|
|
T23 |
123 |
|
T24 |
197 |
|
T25 |
261 |
| auto[1] |
2175585 |
1 |
|
|
T24 |
50 |
|
T1 |
80 |
|
T11 |
67955 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7367780 |
1 |
|
|
T23 |
123 |
|
T24 |
151 |
|
T25 |
261 |
| auto[1] |
5223599 |
1 |
|
|
T24 |
96 |
|
T1 |
130 |
|
T11 |
180212 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1516306 |
1 |
|
|
T24 |
17 |
|
T1 |
26 |
|
T11 |
52929 |
| auto[1] |
auto[0] |
auto[1] |
1086765 |
1 |
|
|
T24 |
15 |
|
T1 |
33 |
|
T11 |
32524 |
| auto[1] |
auto[1] |
auto[0] |
1531708 |
1 |
|
|
T24 |
29 |
|
T1 |
24 |
|
T11 |
59328 |
| auto[1] |
auto[1] |
auto[1] |
1088820 |
1 |
|
|
T24 |
35 |
|
T1 |
47 |
|
T11 |
35431 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |