Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7407810 |
1 |
|
|
T23 |
123 |
|
T24 |
125 |
|
T25 |
261 |
| auto[1] |
5183569 |
1 |
|
|
T24 |
122 |
|
T1 |
121 |
|
T11 |
182244 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10423444 |
1 |
|
|
T23 |
123 |
|
T24 |
185 |
|
T25 |
261 |
| auto[1] |
2167935 |
1 |
|
|
T24 |
62 |
|
T1 |
82 |
|
T11 |
68955 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7394450 |
1 |
|
|
T23 |
123 |
|
T24 |
154 |
|
T25 |
261 |
| auto[1] |
5196929 |
1 |
|
|
T24 |
93 |
|
T1 |
117 |
|
T11 |
186067 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1538795 |
1 |
|
|
T24 |
14 |
|
T1 |
13 |
|
T11 |
59544 |
| auto[1] |
auto[0] |
auto[1] |
1095770 |
1 |
|
|
T24 |
43 |
|
T1 |
34 |
|
T11 |
34319 |
| auto[1] |
auto[1] |
auto[0] |
1490199 |
1 |
|
|
T24 |
17 |
|
T1 |
22 |
|
T11 |
57568 |
| auto[1] |
auto[1] |
auto[1] |
1072165 |
1 |
|
|
T24 |
19 |
|
T1 |
48 |
|
T11 |
34636 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |