Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7375582 |
1 |
|
|
T23 |
123 |
|
T24 |
151 |
|
T25 |
261 |
| auto[1] |
5215797 |
1 |
|
|
T24 |
96 |
|
T1 |
91 |
|
T11 |
185918 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11925902 |
1 |
|
|
T23 |
123 |
|
T24 |
242 |
|
T25 |
261 |
| auto[1] |
665477 |
1 |
|
|
T24 |
5 |
|
T1 |
2 |
|
T11 |
24088 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7369488 |
1 |
|
|
T23 |
123 |
|
T24 |
115 |
|
T25 |
261 |
| auto[1] |
5221891 |
1 |
|
|
T24 |
132 |
|
T1 |
116 |
|
T11 |
190748 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2269079 |
1 |
|
|
T24 |
71 |
|
T1 |
87 |
|
T11 |
80871 |
| auto[1] |
auto[0] |
auto[1] |
331251 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T11 |
11520 |
| auto[1] |
auto[1] |
auto[0] |
2287335 |
1 |
|
|
T24 |
56 |
|
T1 |
27 |
|
T11 |
85789 |
| auto[1] |
auto[1] |
auto[1] |
334226 |
1 |
|
|
T24 |
3 |
|
T11 |
12568 |
|
T15 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |