Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7402783 |
1 |
|
|
T23 |
123 |
|
T24 |
121 |
|
T25 |
261 |
| auto[1] |
5188596 |
1 |
|
|
T24 |
126 |
|
T1 |
153 |
|
T11 |
185796 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10428963 |
1 |
|
|
T23 |
123 |
|
T24 |
208 |
|
T25 |
261 |
| auto[1] |
2162416 |
1 |
|
|
T24 |
39 |
|
T1 |
106 |
|
T11 |
67289 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7400910 |
1 |
|
|
T23 |
123 |
|
T24 |
140 |
|
T25 |
261 |
| auto[1] |
5190469 |
1 |
|
|
T24 |
107 |
|
T1 |
139 |
|
T11 |
181755 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1522239 |
1 |
|
|
T24 |
38 |
|
T1 |
13 |
|
T11 |
54939 |
| auto[1] |
auto[0] |
auto[1] |
1083031 |
1 |
|
|
T24 |
20 |
|
T1 |
10 |
|
T11 |
32726 |
| auto[1] |
auto[1] |
auto[0] |
1505814 |
1 |
|
|
T24 |
30 |
|
T1 |
20 |
|
T11 |
59527 |
| auto[1] |
auto[1] |
auto[1] |
1079385 |
1 |
|
|
T24 |
19 |
|
T1 |
96 |
|
T11 |
34563 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |