Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7363869 |
1 |
|
|
T23 |
123 |
|
T24 |
134 |
|
T25 |
261 |
| auto[1] |
5227510 |
1 |
|
|
T24 |
113 |
|
T1 |
169 |
|
T11 |
179436 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10408066 |
1 |
|
|
T23 |
123 |
|
T24 |
213 |
|
T25 |
261 |
| auto[1] |
2183313 |
1 |
|
|
T24 |
34 |
|
T1 |
59 |
|
T11 |
67248 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7340845 |
1 |
|
|
T23 |
123 |
|
T24 |
173 |
|
T25 |
261 |
| auto[1] |
5250534 |
1 |
|
|
T24 |
74 |
|
T1 |
63 |
|
T11 |
180175 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1536829 |
1 |
|
|
T24 |
28 |
|
T1 |
1 |
|
T11 |
58899 |
| auto[1] |
auto[0] |
auto[1] |
1086904 |
1 |
|
|
T24 |
26 |
|
T1 |
6 |
|
T11 |
34081 |
| auto[1] |
auto[1] |
auto[0] |
1530392 |
1 |
|
|
T24 |
12 |
|
T1 |
3 |
|
T11 |
54028 |
| auto[1] |
auto[1] |
auto[1] |
1096409 |
1 |
|
|
T24 |
8 |
|
T1 |
53 |
|
T11 |
33167 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |