Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7364140 |
1 |
|
|
T23 |
123 |
|
T24 |
132 |
|
T25 |
261 |
| auto[1] |
5227239 |
1 |
|
|
T24 |
115 |
|
T1 |
52 |
|
T11 |
182337 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10416405 |
1 |
|
|
T23 |
123 |
|
T24 |
172 |
|
T25 |
261 |
| auto[1] |
2174974 |
1 |
|
|
T24 |
75 |
|
T1 |
77 |
|
T11 |
68522 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7379831 |
1 |
|
|
T23 |
123 |
|
T24 |
91 |
|
T25 |
261 |
| auto[1] |
5211548 |
1 |
|
|
T24 |
156 |
|
T1 |
115 |
|
T11 |
183252 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1515004 |
1 |
|
|
T24 |
41 |
|
T1 |
26 |
|
T11 |
56351 |
| auto[1] |
auto[0] |
auto[1] |
1089515 |
1 |
|
|
T24 |
24 |
|
T1 |
59 |
|
T11 |
33625 |
| auto[1] |
auto[1] |
auto[0] |
1521570 |
1 |
|
|
T24 |
40 |
|
T1 |
12 |
|
T11 |
58379 |
| auto[1] |
auto[1] |
auto[1] |
1085459 |
1 |
|
|
T24 |
51 |
|
T1 |
18 |
|
T11 |
34897 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |