Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7386059 |
1 |
|
|
T23 |
123 |
|
T24 |
120 |
|
T25 |
261 |
| auto[1] |
5205320 |
1 |
|
|
T24 |
127 |
|
T1 |
84 |
|
T11 |
180552 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11927404 |
1 |
|
|
T23 |
123 |
|
T24 |
242 |
|
T25 |
261 |
| auto[1] |
663975 |
1 |
|
|
T24 |
5 |
|
T1 |
4 |
|
T11 |
23888 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7376444 |
1 |
|
|
T23 |
123 |
|
T24 |
155 |
|
T25 |
261 |
| auto[1] |
5214935 |
1 |
|
|
T24 |
92 |
|
T1 |
112 |
|
T11 |
189148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2280644 |
1 |
|
|
T24 |
49 |
|
T1 |
66 |
|
T11 |
82620 |
| auto[1] |
auto[0] |
auto[1] |
333262 |
1 |
|
|
T24 |
4 |
|
T1 |
4 |
|
T11 |
11980 |
| auto[1] |
auto[1] |
auto[0] |
2270316 |
1 |
|
|
T24 |
38 |
|
T1 |
42 |
|
T11 |
82640 |
| auto[1] |
auto[1] |
auto[1] |
330713 |
1 |
|
|
T24 |
1 |
|
T11 |
11908 |
|
T16 |
2208 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |