Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7376669 |
1 |
|
|
T23 |
123 |
|
T24 |
120 |
|
T25 |
261 |
| auto[1] |
5214710 |
1 |
|
|
T24 |
127 |
|
T1 |
66 |
|
T11 |
179789 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11928667 |
1 |
|
|
T23 |
123 |
|
T24 |
243 |
|
T25 |
261 |
| auto[1] |
662712 |
1 |
|
|
T24 |
4 |
|
T1 |
8 |
|
T11 |
22386 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7375990 |
1 |
|
|
T23 |
123 |
|
T24 |
174 |
|
T25 |
261 |
| auto[1] |
5215389 |
1 |
|
|
T24 |
73 |
|
T1 |
140 |
|
T11 |
180004 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2276937 |
1 |
|
|
T24 |
19 |
|
T1 |
88 |
|
T11 |
79000 |
| auto[1] |
auto[0] |
auto[1] |
330529 |
1 |
|
|
T24 |
1 |
|
T1 |
5 |
|
T11 |
11167 |
| auto[1] |
auto[1] |
auto[0] |
2275740 |
1 |
|
|
T24 |
50 |
|
T1 |
44 |
|
T11 |
78618 |
| auto[1] |
auto[1] |
auto[1] |
332183 |
1 |
|
|
T24 |
3 |
|
T1 |
3 |
|
T11 |
11219 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |