Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7360789 |
1 |
|
|
T23 |
123 |
|
T24 |
89 |
|
T25 |
261 |
| auto[1] |
5230590 |
1 |
|
|
T24 |
158 |
|
T1 |
158 |
|
T11 |
182315 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11927124 |
1 |
|
|
T23 |
123 |
|
T24 |
243 |
|
T25 |
261 |
| auto[1] |
664255 |
1 |
|
|
T24 |
4 |
|
T1 |
2 |
|
T11 |
23210 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7377502 |
1 |
|
|
T23 |
123 |
|
T24 |
147 |
|
T25 |
261 |
| auto[1] |
5213877 |
1 |
|
|
T24 |
100 |
|
T1 |
136 |
|
T11 |
185649 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2258191 |
1 |
|
|
T24 |
45 |
|
T1 |
51 |
|
T11 |
81442 |
| auto[1] |
auto[0] |
auto[1] |
328520 |
1 |
|
|
T24 |
2 |
|
T11 |
11596 |
|
T15 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2291431 |
1 |
|
|
T24 |
51 |
|
T1 |
83 |
|
T11 |
80997 |
| auto[1] |
auto[1] |
auto[1] |
335735 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T11 |
11614 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |