Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7407521 |
1 |
|
|
T23 |
123 |
|
T24 |
161 |
|
T25 |
261 |
| auto[1] |
5183858 |
1 |
|
|
T24 |
86 |
|
T1 |
97 |
|
T11 |
182947 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11930272 |
1 |
|
|
T23 |
123 |
|
T24 |
236 |
|
T25 |
261 |
| auto[1] |
661107 |
1 |
|
|
T24 |
11 |
|
T1 |
7 |
|
T11 |
23361 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7389635 |
1 |
|
|
T23 |
123 |
|
T24 |
139 |
|
T25 |
261 |
| auto[1] |
5201744 |
1 |
|
|
T24 |
108 |
|
T1 |
149 |
|
T11 |
186213 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2274261 |
1 |
|
|
T24 |
66 |
|
T1 |
75 |
|
T11 |
81169 |
| auto[1] |
auto[0] |
auto[1] |
330865 |
1 |
|
|
T24 |
9 |
|
T1 |
5 |
|
T11 |
11622 |
| auto[1] |
auto[1] |
auto[0] |
2266376 |
1 |
|
|
T24 |
31 |
|
T1 |
67 |
|
T11 |
81683 |
| auto[1] |
auto[1] |
auto[1] |
330242 |
1 |
|
|
T24 |
2 |
|
T1 |
2 |
|
T11 |
11739 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |