Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7373391 |
1 |
|
|
T23 |
123 |
|
T24 |
114 |
|
T25 |
261 |
| auto[1] |
5217988 |
1 |
|
|
T24 |
133 |
|
T1 |
133 |
|
T11 |
185151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11927651 |
1 |
|
|
T23 |
123 |
|
T24 |
239 |
|
T25 |
261 |
| auto[1] |
663728 |
1 |
|
|
T24 |
8 |
|
T1 |
4 |
|
T11 |
22000 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7380855 |
1 |
|
|
T23 |
123 |
|
T24 |
136 |
|
T25 |
261 |
| auto[1] |
5210524 |
1 |
|
|
T24 |
111 |
|
T1 |
145 |
|
T11 |
177969 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2270267 |
1 |
|
|
T24 |
50 |
|
T1 |
77 |
|
T11 |
75535 |
| auto[1] |
auto[0] |
auto[1] |
331175 |
1 |
|
|
T24 |
3 |
|
T1 |
2 |
|
T11 |
10532 |
| auto[1] |
auto[1] |
auto[0] |
2276529 |
1 |
|
|
T24 |
53 |
|
T1 |
64 |
|
T11 |
80434 |
| auto[1] |
auto[1] |
auto[1] |
332553 |
1 |
|
|
T24 |
5 |
|
T1 |
2 |
|
T11 |
11468 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |