Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7356759 |
1 |
|
|
T23 |
123 |
|
T24 |
130 |
|
T25 |
261 |
| auto[1] |
5234620 |
1 |
|
|
T24 |
117 |
|
T1 |
58 |
|
T11 |
183892 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11927782 |
1 |
|
|
T23 |
123 |
|
T24 |
236 |
|
T25 |
261 |
| auto[1] |
663597 |
1 |
|
|
T24 |
11 |
|
T1 |
6 |
|
T11 |
23089 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7378258 |
1 |
|
|
T23 |
123 |
|
T24 |
98 |
|
T25 |
261 |
| auto[1] |
5213121 |
1 |
|
|
T24 |
149 |
|
T1 |
115 |
|
T11 |
181983 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2265482 |
1 |
|
|
T24 |
61 |
|
T1 |
85 |
|
T11 |
81127 |
| auto[1] |
auto[0] |
auto[1] |
330293 |
1 |
|
|
T24 |
7 |
|
T1 |
4 |
|
T11 |
11866 |
| auto[1] |
auto[1] |
auto[0] |
2284042 |
1 |
|
|
T24 |
77 |
|
T1 |
24 |
|
T11 |
77767 |
| auto[1] |
auto[1] |
auto[1] |
333304 |
1 |
|
|
T24 |
4 |
|
T1 |
2 |
|
T11 |
11223 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |