cp_pins | cp_stable_cycles | cp_pin_value | cp_filter_en | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[0] |
auto[0] |
52605 |
1 |
|
|
T96 |
2042 |
|
T97 |
956 |
|
T98 |
88 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48220 |
1 |
|
|
T96 |
827 |
|
T97 |
608 |
|
T98 |
174 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[1] |
auto[0] |
52534 |
1 |
|
|
T96 |
1106 |
|
T97 |
1032 |
|
T98 |
132 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[1] |
auto[1] |
49167 |
1 |
|
|
T96 |
722 |
|
T97 |
1229 |
|
T98 |
828 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1658 |
1 |
|
|
T96 |
37 |
|
T97 |
32 |
|
T98 |
7 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T96 |
15 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1671 |
1 |
|
|
T96 |
34 |
|
T97 |
25 |
|
T98 |
9 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1623 |
1 |
|
|
T96 |
37 |
|
T97 |
32 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T96 |
15 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1638 |
1 |
|
|
T96 |
34 |
|
T97 |
25 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1594 |
1 |
|
|
T96 |
36 |
|
T97 |
32 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T96 |
15 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1612 |
1 |
|
|
T96 |
34 |
|
T97 |
25 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T96 |
36 |
|
T97 |
30 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T96 |
15 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1585 |
1 |
|
|
T96 |
34 |
|
T97 |
23 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1529 |
1 |
|
|
T96 |
36 |
|
T97 |
30 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T96 |
15 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1548 |
1 |
|
|
T96 |
34 |
|
T97 |
22 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1489 |
1 |
|
|
T96 |
36 |
|
T97 |
30 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T96 |
15 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1514 |
1 |
|
|
T96 |
33 |
|
T97 |
22 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1467 |
1 |
|
|
T96 |
35 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T96 |
15 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1486 |
1 |
|
|
T96 |
33 |
|
T97 |
21 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1444 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T96 |
15 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1437 |
1 |
|
|
T96 |
30 |
|
T97 |
20 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1417 |
1 |
|
|
T96 |
33 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T96 |
15 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1401 |
1 |
|
|
T96 |
30 |
|
T97 |
21 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1390 |
1 |
|
|
T96 |
33 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T96 |
15 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1360 |
1 |
|
|
T96 |
30 |
|
T97 |
19 |
|
T98 |
8 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1356 |
1 |
|
|
T96 |
32 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
15 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1330 |
1 |
|
|
T96 |
29 |
|
T97 |
18 |
|
T98 |
7 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1332 |
1 |
|
|
T96 |
32 |
|
T97 |
27 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
15 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1295 |
1 |
|
|
T96 |
28 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1297 |
1 |
|
|
T96 |
32 |
|
T97 |
27 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T96 |
15 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1261 |
1 |
|
|
T96 |
27 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1267 |
1 |
|
|
T96 |
32 |
|
T97 |
27 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T96 |
15 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1226 |
1 |
|
|
T96 |
26 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1233 |
1 |
|
|
T96 |
30 |
|
T97 |
26 |
|
T98 |
5 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T96 |
15 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1198 |
1 |
|
|
T96 |
26 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[0] |
auto[0] |
62502 |
1 |
|
|
T96 |
881 |
|
T97 |
1379 |
|
T98 |
206 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[0] |
auto[1] |
40407 |
1 |
|
|
T96 |
871 |
|
T97 |
797 |
|
T98 |
113 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[1] |
auto[0] |
59782 |
1 |
|
|
T96 |
1851 |
|
T97 |
914 |
|
T98 |
819 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[1] |
auto[1] |
40713 |
1 |
|
|
T96 |
835 |
|
T97 |
613 |
|
T98 |
94 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1581 |
1 |
|
|
T96 |
44 |
|
T97 |
40 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1596 |
1 |
|
|
T96 |
41 |
|
T97 |
39 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T96 |
42 |
|
T97 |
40 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1558 |
1 |
|
|
T96 |
38 |
|
T97 |
39 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1529 |
1 |
|
|
T96 |
41 |
|
T97 |
40 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1528 |
1 |
|
|
T96 |
37 |
|
T97 |
39 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1494 |
1 |
|
|
T96 |
40 |
|
T97 |
39 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1497 |
1 |
|
|
T96 |
37 |
|
T97 |
38 |
|
T98 |
4 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1479 |
1 |
|
|
T96 |
41 |
|
T97 |
39 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1465 |
1 |
|
|
T96 |
37 |
|
T97 |
37 |
|
T98 |
4 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1448 |
1 |
|
|
T96 |
40 |
|
T97 |
39 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1435 |
1 |
|
|
T96 |
37 |
|
T97 |
35 |
|
T98 |
3 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1422 |
1 |
|
|
T96 |
40 |
|
T97 |
38 |
|
T98 |
6 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1400 |
1 |
|
|
T96 |
35 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1393 |
1 |
|
|
T96 |
38 |
|
T97 |
37 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1371 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
2 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1369 |
1 |
|
|
T96 |
37 |
|
T97 |
37 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1335 |
1 |
|
|
T96 |
35 |
|
T97 |
29 |
|
T98 |
2 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1341 |
1 |
|
|
T96 |
36 |
|
T97 |
36 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1308 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
2 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1311 |
1 |
|
|
T96 |
34 |
|
T97 |
35 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1277 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
2 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1277 |
1 |
|
|
T96 |
33 |
|
T97 |
34 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1243 |
1 |
|
|
T96 |
31 |
|
T97 |
27 |
|
T98 |
2 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1241 |
1 |
|
|
T96 |
33 |
|
T97 |
32 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1210 |
1 |
|
|
T96 |
30 |
|
T97 |
25 |
|
T98 |
2 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1207 |
1 |
|
|
T96 |
32 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1182 |
1 |
|
|
T96 |
29 |
|
T97 |
24 |
|
T98 |
2 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1175 |
1 |
|
|
T96 |
32 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1138 |
1 |
|
|
T96 |
26 |
|
T97 |
23 |
|
T98 |
2 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[0] |
auto[0] |
62014 |
1 |
|
|
T96 |
1625 |
|
T97 |
1899 |
|
T98 |
216 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46828 |
1 |
|
|
T96 |
1011 |
|
T97 |
392 |
|
T98 |
131 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[1] |
auto[0] |
54453 |
1 |
|
|
T96 |
1073 |
|
T97 |
1203 |
|
T98 |
230 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[1] |
auto[1] |
40467 |
1 |
|
|
T96 |
723 |
|
T97 |
325 |
|
T98 |
692 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
730 |
1 |
|
|
T96 |
18 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1577 |
1 |
|
|
T96 |
43 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
735 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1563 |
1 |
|
|
T96 |
36 |
|
T97 |
24 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
730 |
1 |
|
|
T96 |
18 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T96 |
43 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
735 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1530 |
1 |
|
|
T96 |
36 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
730 |
1 |
|
|
T96 |
18 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1521 |
1 |
|
|
T96 |
41 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
735 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1508 |
1 |
|
|
T96 |
36 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
730 |
1 |
|
|
T96 |
18 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1491 |
1 |
|
|
T96 |
41 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
735 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1478 |
1 |
|
|
T96 |
36 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1466 |
1 |
|
|
T96 |
41 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1449 |
1 |
|
|
T96 |
33 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1439 |
1 |
|
|
T96 |
40 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
734 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1423 |
1 |
|
|
T96 |
33 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1420 |
1 |
|
|
T96 |
40 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1394 |
1 |
|
|
T96 |
33 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1388 |
1 |
|
|
T96 |
40 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1355 |
1 |
|
|
T96 |
32 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1349 |
1 |
|
|
T96 |
39 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1323 |
1 |
|
|
T96 |
31 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1324 |
1 |
|
|
T96 |
39 |
|
T97 |
17 |
|
T98 |
2 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1296 |
1 |
|
|
T96 |
30 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1283 |
1 |
|
|
T96 |
35 |
|
T97 |
17 |
|
T98 |
2 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1263 |
1 |
|
|
T96 |
29 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1256 |
1 |
|
|
T96 |
33 |
|
T97 |
17 |
|
T98 |
2 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1234 |
1 |
|
|
T96 |
27 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1224 |
1 |
|
|
T96 |
32 |
|
T97 |
17 |
|
T98 |
2 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1205 |
1 |
|
|
T96 |
27 |
|
T97 |
16 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T96 |
32 |
|
T97 |
17 |
|
T98 |
2 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1180 |
1 |
|
|
T96 |
25 |
|
T97 |
16 |
|
T98 |
3 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
17 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1174 |
1 |
|
|
T96 |
32 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
24 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1150 |
1 |
|
|
T96 |
25 |
|
T97 |
16 |
|
T98 |
3 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[0] |
auto[0] |
52247 |
1 |
|
|
T96 |
1345 |
|
T97 |
2029 |
|
T98 |
307 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[0] |
auto[1] |
50893 |
1 |
|
|
T96 |
570 |
|
T97 |
542 |
|
T98 |
808 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[1] |
auto[0] |
54969 |
1 |
|
|
T96 |
1312 |
|
T97 |
719 |
|
T98 |
40 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45621 |
1 |
|
|
T96 |
1473 |
|
T97 |
594 |
|
T98 |
110 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1652 |
1 |
|
|
T96 |
37 |
|
T97 |
28 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1662 |
1 |
|
|
T96 |
38 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1621 |
1 |
|
|
T96 |
36 |
|
T97 |
27 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1626 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1598 |
1 |
|
|
T96 |
36 |
|
T97 |
26 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1590 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1569 |
1 |
|
|
T96 |
36 |
|
T97 |
26 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1568 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1550 |
1 |
|
|
T96 |
35 |
|
T97 |
24 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1529 |
1 |
|
|
T96 |
34 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1514 |
1 |
|
|
T96 |
33 |
|
T97 |
24 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1504 |
1 |
|
|
T96 |
33 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1481 |
1 |
|
|
T96 |
33 |
|
T97 |
24 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
648 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1472 |
1 |
|
|
T96 |
32 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1445 |
1 |
|
|
T96 |
31 |
|
T97 |
24 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
648 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1445 |
1 |
|
|
T96 |
30 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1414 |
1 |
|
|
T96 |
31 |
|
T97 |
24 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
15 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1412 |
1 |
|
|
T96 |
30 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1374 |
1 |
|
|
T96 |
30 |
|
T97 |
23 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
15 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1376 |
1 |
|
|
T96 |
28 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
657 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1329 |
1 |
|
|
T96 |
28 |
|
T97 |
22 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
15 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1344 |
1 |
|
|
T96 |
28 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
657 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1289 |
1 |
|
|
T96 |
26 |
|
T97 |
22 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
15 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1320 |
1 |
|
|
T96 |
28 |
|
T97 |
28 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
657 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1248 |
1 |
|
|
T96 |
25 |
|
T97 |
20 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
642 |
1 |
|
|
T96 |
15 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1285 |
1 |
|
|
T96 |
27 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
657 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1217 |
1 |
|
|
T96 |
22 |
|
T97 |
20 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
642 |
1 |
|
|
T96 |
15 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1250 |
1 |
|
|
T96 |
26 |
|
T97 |
26 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
656 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
2 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T96 |
22 |
|
T97 |
19 |
|
T98 |
9 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
642 |
1 |
|
|
T96 |
15 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1219 |
1 |
|
|
T96 |
26 |
|
T97 |
26 |
|
T98 |
2 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57716 |
1 |
|
|
T96 |
761 |
|
T97 |
1530 |
|
T98 |
216 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47978 |
1 |
|
|
T96 |
1610 |
|
T97 |
793 |
|
T98 |
102 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[1] |
auto[0] |
51323 |
1 |
|
|
T96 |
1002 |
|
T97 |
716 |
|
T98 |
187 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[1] |
auto[1] |
47429 |
1 |
|
|
T96 |
1013 |
|
T97 |
764 |
|
T98 |
720 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1602 |
1 |
|
|
T96 |
49 |
|
T97 |
34 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1624 |
1 |
|
|
T96 |
43 |
|
T97 |
38 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1572 |
1 |
|
|
T96 |
49 |
|
T97 |
33 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1584 |
1 |
|
|
T96 |
43 |
|
T97 |
38 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1540 |
1 |
|
|
T96 |
49 |
|
T97 |
33 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1541 |
1 |
|
|
T96 |
42 |
|
T97 |
37 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1511 |
1 |
|
|
T96 |
49 |
|
T97 |
33 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1508 |
1 |
|
|
T96 |
40 |
|
T97 |
35 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1484 |
1 |
|
|
T96 |
47 |
|
T97 |
33 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1477 |
1 |
|
|
T96 |
40 |
|
T97 |
35 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T96 |
45 |
|
T97 |
33 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1449 |
1 |
|
|
T96 |
40 |
|
T97 |
33 |
|
T98 |
7 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1445 |
1 |
|
|
T96 |
44 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1400 |
1 |
|
|
T96 |
40 |
|
T97 |
31 |
|
T98 |
6 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1417 |
1 |
|
|
T96 |
42 |
|
T97 |
32 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1376 |
1 |
|
|
T96 |
40 |
|
T97 |
31 |
|
T98 |
6 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1397 |
1 |
|
|
T96 |
40 |
|
T97 |
32 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1345 |
1 |
|
|
T96 |
38 |
|
T97 |
30 |
|
T98 |
6 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1357 |
1 |
|
|
T96 |
40 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1309 |
1 |
|
|
T96 |
36 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1326 |
1 |
|
|
T96 |
38 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
661 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1274 |
1 |
|
|
T96 |
35 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1294 |
1 |
|
|
T96 |
38 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
661 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1245 |
1 |
|
|
T96 |
35 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1263 |
1 |
|
|
T96 |
36 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1213 |
1 |
|
|
T96 |
35 |
|
T97 |
25 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1237 |
1 |
|
|
T96 |
36 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1178 |
1 |
|
|
T96 |
35 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
19 |
|
T97 |
8 |
|
T98 |
5 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1147 |
1 |
|
|
T96 |
31 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[0] |
auto[0] |
51666 |
1 |
|
|
T96 |
869 |
|
T97 |
1535 |
|
T98 |
161 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49702 |
1 |
|
|
T96 |
994 |
|
T97 |
939 |
|
T98 |
58 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55443 |
1 |
|
|
T96 |
1864 |
|
T97 |
624 |
|
T98 |
897 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45884 |
1 |
|
|
T96 |
929 |
|
T97 |
608 |
|
T98 |
158 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
665 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1715 |
1 |
|
|
T96 |
40 |
|
T97 |
42 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T96 |
13 |
|
T97 |
7 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1703 |
1 |
|
|
T96 |
40 |
|
T97 |
44 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
665 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1674 |
1 |
|
|
T96 |
40 |
|
T97 |
42 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T96 |
13 |
|
T97 |
7 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1661 |
1 |
|
|
T96 |
39 |
|
T97 |
44 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
663 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1642 |
1 |
|
|
T96 |
40 |
|
T97 |
41 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T96 |
13 |
|
T97 |
7 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1627 |
1 |
|
|
T96 |
39 |
|
T97 |
44 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
663 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1611 |
1 |
|
|
T96 |
40 |
|
T97 |
41 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T96 |
13 |
|
T97 |
7 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1581 |
1 |
|
|
T96 |
38 |
|
T97 |
43 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
656 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1578 |
1 |
|
|
T96 |
41 |
|
T97 |
39 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T96 |
13 |
|
T97 |
7 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1549 |
1 |
|
|
T96 |
36 |
|
T97 |
40 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
656 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1539 |
1 |
|
|
T96 |
40 |
|
T97 |
39 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T96 |
13 |
|
T97 |
7 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1521 |
1 |
|
|
T96 |
36 |
|
T97 |
37 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
651 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1512 |
1 |
|
|
T96 |
38 |
|
T97 |
38 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T96 |
13 |
|
T97 |
7 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1485 |
1 |
|
|
T96 |
35 |
|
T97 |
36 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
651 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1477 |
1 |
|
|
T96 |
36 |
|
T97 |
38 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T96 |
13 |
|
T97 |
7 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1449 |
1 |
|
|
T96 |
33 |
|
T97 |
35 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
648 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1433 |
1 |
|
|
T96 |
35 |
|
T97 |
38 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T96 |
13 |
|
T97 |
6 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1420 |
1 |
|
|
T96 |
32 |
|
T97 |
34 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
648 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1396 |
1 |
|
|
T96 |
34 |
|
T97 |
37 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T96 |
13 |
|
T97 |
6 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1393 |
1 |
|
|
T96 |
32 |
|
T97 |
32 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
647 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1363 |
1 |
|
|
T96 |
33 |
|
T97 |
37 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
663 |
1 |
|
|
T96 |
13 |
|
T97 |
6 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1361 |
1 |
|
|
T96 |
32 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
647 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1333 |
1 |
|
|
T96 |
33 |
|
T97 |
35 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
663 |
1 |
|
|
T96 |
13 |
|
T97 |
6 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1332 |
1 |
|
|
T96 |
31 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
646 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1306 |
1 |
|
|
T96 |
31 |
|
T97 |
35 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T96 |
13 |
|
T97 |
6 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1292 |
1 |
|
|
T96 |
31 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
646 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1274 |
1 |
|
|
T96 |
31 |
|
T97 |
35 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T96 |
13 |
|
T97 |
6 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1260 |
1 |
|
|
T96 |
30 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
646 |
1 |
|
|
T96 |
12 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1243 |
1 |
|
|
T96 |
31 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T96 |
13 |
|
T97 |
6 |
|
T98 |
5 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1239 |
1 |
|
|
T96 |
29 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58604 |
1 |
|
|
T96 |
1397 |
|
T97 |
1089 |
|
T98 |
199 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49959 |
1 |
|
|
T96 |
1438 |
|
T97 |
1579 |
|
T98 |
53 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[1] |
auto[0] |
48665 |
1 |
|
|
T96 |
1217 |
|
T97 |
844 |
|
T98 |
185 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44825 |
1 |
|
|
T96 |
746 |
|
T97 |
402 |
|
T98 |
875 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1665 |
1 |
|
|
T96 |
27 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T96 |
18 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1641 |
1 |
|
|
T96 |
29 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1635 |
1 |
|
|
T96 |
26 |
|
T97 |
29 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T96 |
18 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1612 |
1 |
|
|
T96 |
28 |
|
T97 |
21 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1602 |
1 |
|
|
T96 |
26 |
|
T97 |
28 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T96 |
18 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1588 |
1 |
|
|
T96 |
27 |
|
T97 |
21 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1577 |
1 |
|
|
T96 |
25 |
|
T97 |
28 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T96 |
18 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1556 |
1 |
|
|
T96 |
27 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1554 |
1 |
|
|
T96 |
25 |
|
T97 |
26 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T96 |
18 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1524 |
1 |
|
|
T96 |
25 |
|
T97 |
19 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1526 |
1 |
|
|
T96 |
24 |
|
T97 |
26 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T96 |
18 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1494 |
1 |
|
|
T96 |
25 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1496 |
1 |
|
|
T96 |
24 |
|
T97 |
26 |
|
T98 |
2 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T96 |
18 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1451 |
1 |
|
|
T96 |
24 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T96 |
23 |
|
T97 |
26 |
|
T98 |
2 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T96 |
18 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1416 |
1 |
|
|
T96 |
24 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
698 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1432 |
1 |
|
|
T96 |
22 |
|
T97 |
24 |
|
T98 |
2 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T96 |
18 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1385 |
1 |
|
|
T96 |
24 |
|
T97 |
19 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
698 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1395 |
1 |
|
|
T96 |
21 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T96 |
18 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1352 |
1 |
|
|
T96 |
24 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1354 |
1 |
|
|
T96 |
20 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T96 |
18 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1318 |
1 |
|
|
T96 |
23 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1322 |
1 |
|
|
T96 |
19 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T96 |
18 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1280 |
1 |
|
|
T96 |
23 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1283 |
1 |
|
|
T96 |
19 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T96 |
18 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1251 |
1 |
|
|
T96 |
23 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T96 |
18 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T96 |
18 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1219 |
1 |
|
|
T96 |
23 |
|
T97 |
13 |
|
T98 |
6 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1213 |
1 |
|
|
T96 |
18 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T96 |
18 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1195 |
1 |
|
|
T96 |
22 |
|
T97 |
13 |
|
T98 |
6 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53902 |
1 |
|
|
T96 |
1665 |
|
T97 |
1093 |
|
T98 |
410 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49513 |
1 |
|
|
T96 |
1459 |
|
T97 |
791 |
|
T98 |
40 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56462 |
1 |
|
|
T96 |
988 |
|
T97 |
733 |
|
T98 |
783 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44185 |
1 |
|
|
T96 |
530 |
|
T97 |
1151 |
|
T98 |
80 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
23 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1574 |
1 |
|
|
T96 |
30 |
|
T97 |
33 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1574 |
1 |
|
|
T96 |
32 |
|
T97 |
31 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
23 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T96 |
30 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1548 |
1 |
|
|
T96 |
32 |
|
T97 |
29 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
23 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1517 |
1 |
|
|
T96 |
30 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1513 |
1 |
|
|
T96 |
32 |
|
T97 |
28 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
23 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1490 |
1 |
|
|
T96 |
29 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
722 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1487 |
1 |
|
|
T96 |
31 |
|
T97 |
27 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T96 |
30 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1447 |
1 |
|
|
T96 |
31 |
|
T97 |
26 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1437 |
1 |
|
|
T96 |
28 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1422 |
1 |
|
|
T96 |
30 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1403 |
1 |
|
|
T96 |
28 |
|
T97 |
31 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1391 |
1 |
|
|
T96 |
28 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1376 |
1 |
|
|
T96 |
28 |
|
T97 |
30 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1351 |
1 |
|
|
T96 |
27 |
|
T97 |
23 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1345 |
1 |
|
|
T96 |
27 |
|
T97 |
30 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1314 |
1 |
|
|
T96 |
25 |
|
T97 |
22 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1319 |
1 |
|
|
T96 |
26 |
|
T97 |
30 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1293 |
1 |
|
|
T96 |
24 |
|
T97 |
21 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1282 |
1 |
|
|
T96 |
25 |
|
T97 |
29 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1264 |
1 |
|
|
T96 |
23 |
|
T97 |
21 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1252 |
1 |
|
|
T96 |
25 |
|
T97 |
29 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1242 |
1 |
|
|
T96 |
23 |
|
T97 |
20 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1224 |
1 |
|
|
T96 |
25 |
|
T97 |
27 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1206 |
1 |
|
|
T96 |
22 |
|
T97 |
19 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T96 |
25 |
|
T97 |
27 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1179 |
1 |
|
|
T96 |
22 |
|
T97 |
19 |
|
T98 |
1 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
22 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1162 |
1 |
|
|
T96 |
25 |
|
T97 |
26 |
|
T98 |
2 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
7 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1144 |
1 |
|
|
T96 |
22 |
|
T97 |
19 |
|
T98 |
1 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56030 |
1 |
|
|
T96 |
972 |
|
T97 |
716 |
|
T98 |
775 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49150 |
1 |
|
|
T96 |
1475 |
|
T97 |
1451 |
|
T98 |
130 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53465 |
1 |
|
|
T96 |
1353 |
|
T97 |
939 |
|
T98 |
339 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45857 |
1 |
|
|
T96 |
758 |
|
T97 |
712 |
|
T98 |
86 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1562 |
1 |
|
|
T96 |
37 |
|
T97 |
34 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1581 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1536 |
1 |
|
|
T96 |
35 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1557 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1508 |
1 |
|
|
T96 |
35 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1530 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1473 |
1 |
|
|
T96 |
34 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1498 |
1 |
|
|
T96 |
34 |
|
T97 |
31 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1452 |
1 |
|
|
T96 |
33 |
|
T97 |
32 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
700 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1468 |
1 |
|
|
T96 |
33 |
|
T97 |
31 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1427 |
1 |
|
|
T96 |
33 |
|
T97 |
31 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
700 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1432 |
1 |
|
|
T96 |
33 |
|
T97 |
31 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1396 |
1 |
|
|
T96 |
32 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1395 |
1 |
|
|
T96 |
31 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1354 |
1 |
|
|
T96 |
32 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1366 |
1 |
|
|
T96 |
30 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T96 |
19 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1318 |
1 |
|
|
T96 |
32 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1332 |
1 |
|
|
T96 |
30 |
|
T97 |
24 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T96 |
19 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1285 |
1 |
|
|
T96 |
31 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1301 |
1 |
|
|
T96 |
29 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T96 |
19 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T96 |
28 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1261 |
1 |
|
|
T96 |
28 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T96 |
19 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1226 |
1 |
|
|
T96 |
27 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1233 |
1 |
|
|
T96 |
28 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T96 |
19 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1198 |
1 |
|
|
T96 |
26 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1205 |
1 |
|
|
T96 |
27 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
716 |
1 |
|
|
T96 |
19 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1163 |
1 |
|
|
T96 |
25 |
|
T97 |
28 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1179 |
1 |
|
|
T96 |
27 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T96 |
19 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1138 |
1 |
|
|
T96 |
24 |
|
T97 |
28 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T96 |
21 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1147 |
1 |
|
|
T96 |
26 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53852 |
1 |
|
|
T96 |
1130 |
|
T97 |
884 |
|
T98 |
179 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46284 |
1 |
|
|
T96 |
628 |
|
T97 |
666 |
|
T98 |
42 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[1] |
auto[0] |
58295 |
1 |
|
|
T96 |
1121 |
|
T97 |
1195 |
|
T98 |
427 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44161 |
1 |
|
|
T96 |
1641 |
|
T97 |
951 |
|
T98 |
695 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
6 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1655 |
1 |
|
|
T96 |
38 |
|
T97 |
38 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1646 |
1 |
|
|
T96 |
41 |
|
T97 |
39 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
6 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1631 |
1 |
|
|
T96 |
38 |
|
T97 |
38 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1623 |
1 |
|
|
T96 |
40 |
|
T97 |
39 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
6 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1601 |
1 |
|
|
T96 |
38 |
|
T97 |
37 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
710 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1597 |
1 |
|
|
T96 |
40 |
|
T97 |
38 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
6 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1580 |
1 |
|
|
T96 |
37 |
|
T97 |
37 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
710 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1559 |
1 |
|
|
T96 |
39 |
|
T97 |
37 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
6 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1556 |
1 |
|
|
T96 |
38 |
|
T97 |
36 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
708 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1516 |
1 |
|
|
T96 |
38 |
|
T97 |
35 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
6 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1518 |
1 |
|
|
T96 |
34 |
|
T97 |
36 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
708 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1488 |
1 |
|
|
T96 |
37 |
|
T97 |
35 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1479 |
1 |
|
|
T96 |
33 |
|
T97 |
34 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1453 |
1 |
|
|
T96 |
37 |
|
T97 |
33 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1452 |
1 |
|
|
T96 |
32 |
|
T97 |
32 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1416 |
1 |
|
|
T96 |
36 |
|
T97 |
33 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1404 |
1 |
|
|
T96 |
30 |
|
T97 |
31 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1390 |
1 |
|
|
T96 |
36 |
|
T97 |
33 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1364 |
1 |
|
|
T96 |
30 |
|
T97 |
31 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1360 |
1 |
|
|
T96 |
35 |
|
T97 |
32 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1330 |
1 |
|
|
T96 |
28 |
|
T97 |
28 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1330 |
1 |
|
|
T96 |
35 |
|
T97 |
32 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1302 |
1 |
|
|
T96 |
27 |
|
T97 |
25 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T96 |
17 |
|
T97 |
12 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1307 |
1 |
|
|
T96 |
35 |
|
T97 |
32 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1262 |
1 |
|
|
T96 |
26 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1274 |
1 |
|
|
T96 |
34 |
|
T97 |
31 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1235 |
1 |
|
|
T96 |
25 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1233 |
1 |
|
|
T96 |
33 |
|
T97 |
31 |
|
T98 |
3 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T96 |
19 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T96 |
25 |
|
T97 |
23 |
|
T98 |
1 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1205 |
1 |
|
|
T96 |
32 |
|
T97 |
31 |
|
T98 |
3 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[0] |
auto[0] |
55005 |
1 |
|
|
T96 |
1126 |
|
T97 |
1212 |
|
T98 |
113 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48503 |
1 |
|
|
T96 |
1599 |
|
T97 |
1413 |
|
T98 |
122 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55749 |
1 |
|
|
T96 |
890 |
|
T97 |
713 |
|
T98 |
286 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43561 |
1 |
|
|
T96 |
1006 |
|
T97 |
710 |
|
T98 |
766 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1678 |
1 |
|
|
T96 |
37 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1657 |
1 |
|
|
T96 |
40 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1652 |
1 |
|
|
T96 |
36 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1617 |
1 |
|
|
T96 |
39 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1624 |
1 |
|
|
T96 |
35 |
|
T97 |
24 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
708 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1577 |
1 |
|
|
T96 |
39 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1594 |
1 |
|
|
T96 |
35 |
|
T97 |
24 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
708 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1541 |
1 |
|
|
T96 |
38 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T96 |
35 |
|
T97 |
24 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1519 |
1 |
|
|
T96 |
37 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1526 |
1 |
|
|
T96 |
35 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1486 |
1 |
|
|
T96 |
35 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1489 |
1 |
|
|
T96 |
35 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1440 |
1 |
|
|
T96 |
34 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T96 |
17 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1448 |
1 |
|
|
T96 |
35 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1409 |
1 |
|
|
T96 |
34 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T96 |
16 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1421 |
1 |
|
|
T96 |
34 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1384 |
1 |
|
|
T96 |
33 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T96 |
16 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1391 |
1 |
|
|
T96 |
34 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1346 |
1 |
|
|
T96 |
32 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T96 |
16 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1355 |
1 |
|
|
T96 |
34 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1317 |
1 |
|
|
T96 |
31 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T96 |
16 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1317 |
1 |
|
|
T96 |
34 |
|
T97 |
19 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1271 |
1 |
|
|
T96 |
31 |
|
T97 |
24 |
|
T98 |
3 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
672 |
1 |
|
|
T96 |
16 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1285 |
1 |
|
|
T96 |
33 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1231 |
1 |
|
|
T96 |
30 |
|
T97 |
24 |
|
T98 |
3 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
672 |
1 |
|
|
T96 |
16 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T96 |
32 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1205 |
1 |
|
|
T96 |
30 |
|
T97 |
24 |
|
T98 |
3 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T96 |
16 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1212 |
1 |
|
|
T96 |
31 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T96 |
13 |
|
T97 |
9 |
|
T98 |
5 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1174 |
1 |
|
|
T96 |
29 |
|
T97 |
23 |
|
T98 |
3 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57667 |
1 |
|
|
T96 |
1480 |
|
T97 |
1970 |
|
T98 |
160 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45746 |
1 |
|
|
T96 |
1440 |
|
T97 |
465 |
|
T98 |
736 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[1] |
auto[0] |
54992 |
1 |
|
|
T96 |
935 |
|
T97 |
608 |
|
T98 |
253 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44909 |
1 |
|
|
T96 |
788 |
|
T97 |
798 |
|
T98 |
139 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
678 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1652 |
1 |
|
|
T96 |
37 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1657 |
1 |
|
|
T96 |
37 |
|
T97 |
31 |
|
T98 |
6 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
678 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1616 |
1 |
|
|
T96 |
36 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1623 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1592 |
1 |
|
|
T96 |
36 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1607 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1561 |
1 |
|
|
T96 |
36 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1583 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
672 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1536 |
1 |
|
|
T96 |
34 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1559 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
672 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1497 |
1 |
|
|
T96 |
33 |
|
T97 |
24 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1531 |
1 |
|
|
T96 |
34 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
668 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1469 |
1 |
|
|
T96 |
32 |
|
T97 |
24 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
659 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1499 |
1 |
|
|
T96 |
34 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
668 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1435 |
1 |
|
|
T96 |
31 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
659 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1471 |
1 |
|
|
T96 |
34 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
665 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1392 |
1 |
|
|
T96 |
31 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1428 |
1 |
|
|
T96 |
33 |
|
T97 |
31 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
665 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1363 |
1 |
|
|
T96 |
30 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1396 |
1 |
|
|
T96 |
31 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1321 |
1 |
|
|
T96 |
28 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1363 |
1 |
|
|
T96 |
30 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1284 |
1 |
|
|
T96 |
27 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1333 |
1 |
|
|
T96 |
30 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T96 |
25 |
|
T97 |
17 |
|
T98 |
2 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
652 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1303 |
1 |
|
|
T96 |
29 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1222 |
1 |
|
|
T96 |
24 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
652 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1275 |
1 |
|
|
T96 |
29 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
5 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1188 |
1 |
|
|
T96 |
24 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
652 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1241 |
1 |
|
|
T96 |
28 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53323 |
1 |
|
|
T96 |
794 |
|
T97 |
996 |
|
T98 |
687 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[0] |
auto[1] |
42325 |
1 |
|
|
T96 |
1236 |
|
T97 |
504 |
|
T98 |
195 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57559 |
1 |
|
|
T96 |
1594 |
|
T97 |
1787 |
|
T98 |
193 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[1] |
auto[1] |
49214 |
1 |
|
|
T96 |
883 |
|
T97 |
632 |
|
T98 |
131 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
700 |
1 |
|
|
T96 |
11 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1667 |
1 |
|
|
T96 |
47 |
|
T97 |
22 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1686 |
1 |
|
|
T96 |
43 |
|
T97 |
25 |
|
T98 |
10 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
700 |
1 |
|
|
T96 |
11 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1638 |
1 |
|
|
T96 |
46 |
|
T97 |
21 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1660 |
1 |
|
|
T96 |
43 |
|
T97 |
25 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
700 |
1 |
|
|
T96 |
11 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1606 |
1 |
|
|
T96 |
45 |
|
T97 |
21 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1620 |
1 |
|
|
T96 |
43 |
|
T97 |
25 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
700 |
1 |
|
|
T96 |
11 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1565 |
1 |
|
|
T96 |
45 |
|
T97 |
21 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1587 |
1 |
|
|
T96 |
43 |
|
T97 |
25 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1535 |
1 |
|
|
T96 |
44 |
|
T97 |
21 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1562 |
1 |
|
|
T96 |
42 |
|
T97 |
25 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1499 |
1 |
|
|
T96 |
44 |
|
T97 |
19 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1527 |
1 |
|
|
T96 |
40 |
|
T97 |
24 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1479 |
1 |
|
|
T96 |
43 |
|
T97 |
19 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1492 |
1 |
|
|
T96 |
39 |
|
T97 |
22 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1447 |
1 |
|
|
T96 |
43 |
|
T97 |
19 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1463 |
1 |
|
|
T96 |
38 |
|
T97 |
22 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1412 |
1 |
|
|
T96 |
41 |
|
T97 |
19 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T96 |
15 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1435 |
1 |
|
|
T96 |
36 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1387 |
1 |
|
|
T96 |
41 |
|
T97 |
17 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T96 |
15 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1403 |
1 |
|
|
T96 |
36 |
|
T97 |
22 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1351 |
1 |
|
|
T96 |
41 |
|
T97 |
15 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T96 |
15 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1371 |
1 |
|
|
T96 |
34 |
|
T97 |
22 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1317 |
1 |
|
|
T96 |
41 |
|
T97 |
15 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T96 |
15 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1332 |
1 |
|
|
T96 |
34 |
|
T97 |
21 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1282 |
1 |
|
|
T96 |
39 |
|
T97 |
15 |
|
T98 |
9 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T96 |
15 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1304 |
1 |
|
|
T96 |
33 |
|
T97 |
21 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1244 |
1 |
|
|
T96 |
38 |
|
T97 |
14 |
|
T98 |
8 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T96 |
15 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1283 |
1 |
|
|
T96 |
33 |
|
T97 |
21 |
|
T98 |
7 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
10 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1202 |
1 |
|
|
T96 |
37 |
|
T97 |
14 |
|
T98 |
8 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T96 |
15 |
|
T97 |
15 |
|
T98 |
2 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1258 |
1 |
|
|
T96 |
33 |
|
T97 |
21 |
|
T98 |
6 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57174 |
1 |
|
|
T96 |
1492 |
|
T97 |
700 |
|
T98 |
94 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47806 |
1 |
|
|
T96 |
1116 |
|
T97 |
486 |
|
T98 |
260 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55494 |
1 |
|
|
T96 |
885 |
|
T97 |
2219 |
|
T98 |
730 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43367 |
1 |
|
|
T96 |
997 |
|
T97 |
594 |
|
T98 |
89 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1595 |
1 |
|
|
T96 |
46 |
|
T97 |
25 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1620 |
1 |
|
|
T96 |
46 |
|
T97 |
22 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T96 |
45 |
|
T97 |
25 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1581 |
1 |
|
|
T96 |
46 |
|
T97 |
22 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T96 |
45 |
|
T97 |
24 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1548 |
1 |
|
|
T96 |
44 |
|
T97 |
20 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T96 |
14 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1504 |
1 |
|
|
T96 |
44 |
|
T97 |
24 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1521 |
1 |
|
|
T96 |
44 |
|
T97 |
20 |
|
T98 |
11 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1474 |
1 |
|
|
T96 |
45 |
|
T97 |
24 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1482 |
1 |
|
|
T96 |
42 |
|
T97 |
20 |
|
T98 |
11 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1438 |
1 |
|
|
T96 |
45 |
|
T97 |
24 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1457 |
1 |
|
|
T96 |
39 |
|
T97 |
20 |
|
T98 |
10 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1414 |
1 |
|
|
T96 |
45 |
|
T97 |
22 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1431 |
1 |
|
|
T96 |
37 |
|
T97 |
20 |
|
T98 |
10 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1370 |
1 |
|
|
T96 |
44 |
|
T97 |
22 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1399 |
1 |
|
|
T96 |
36 |
|
T97 |
20 |
|
T98 |
9 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1332 |
1 |
|
|
T96 |
43 |
|
T97 |
22 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1365 |
1 |
|
|
T96 |
35 |
|
T97 |
18 |
|
T98 |
9 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1309 |
1 |
|
|
T96 |
43 |
|
T97 |
21 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1338 |
1 |
|
|
T96 |
34 |
|
T97 |
18 |
|
T98 |
7 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1278 |
1 |
|
|
T96 |
43 |
|
T97 |
21 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1312 |
1 |
|
|
T96 |
33 |
|
T97 |
18 |
|
T98 |
7 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1245 |
1 |
|
|
T96 |
41 |
|
T97 |
20 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1287 |
1 |
|
|
T96 |
32 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1218 |
1 |
|
|
T96 |
40 |
|
T97 |
19 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1259 |
1 |
|
|
T96 |
31 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T96 |
40 |
|
T97 |
19 |
|
T98 |
12 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1229 |
1 |
|
|
T96 |
30 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1166 |
1 |
|
|
T96 |
40 |
|
T97 |
19 |
|
T98 |
11 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T96 |
13 |
|
T97 |
16 |
|
T98 |
2 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1192 |
1 |
|
|
T96 |
29 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53714 |
1 |
|
|
T96 |
978 |
|
T97 |
980 |
|
T98 |
238 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[0] |
auto[1] |
43879 |
1 |
|
|
T96 |
1517 |
|
T97 |
1331 |
|
T98 |
749 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55852 |
1 |
|
|
T96 |
902 |
|
T97 |
1025 |
|
T98 |
129 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[1] |
auto[1] |
49692 |
1 |
|
|
T96 |
1210 |
|
T97 |
575 |
|
T98 |
164 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1688 |
1 |
|
|
T96 |
41 |
|
T97 |
24 |
|
T98 |
6 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1690 |
1 |
|
|
T96 |
41 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1651 |
1 |
|
|
T96 |
41 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1661 |
1 |
|
|
T96 |
41 |
|
T97 |
24 |
|
T98 |
6 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
658 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1610 |
1 |
|
|
T96 |
41 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
659 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1627 |
1 |
|
|
T96 |
41 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
658 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1572 |
1 |
|
|
T96 |
40 |
|
T97 |
22 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
659 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1595 |
1 |
|
|
T96 |
41 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
653 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1543 |
1 |
|
|
T96 |
40 |
|
T97 |
22 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
658 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1568 |
1 |
|
|
T96 |
41 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
653 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1514 |
1 |
|
|
T96 |
37 |
|
T97 |
22 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
658 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1532 |
1 |
|
|
T96 |
41 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1481 |
1 |
|
|
T96 |
36 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
650 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1508 |
1 |
|
|
T96 |
40 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1445 |
1 |
|
|
T96 |
35 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
650 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1488 |
1 |
|
|
T96 |
40 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
647 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1417 |
1 |
|
|
T96 |
34 |
|
T97 |
22 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
646 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1456 |
1 |
|
|
T96 |
39 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
647 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1380 |
1 |
|
|
T96 |
34 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
646 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1422 |
1 |
|
|
T96 |
38 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
645 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1351 |
1 |
|
|
T96 |
32 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
646 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1386 |
1 |
|
|
T96 |
37 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
645 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1317 |
1 |
|
|
T96 |
31 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
646 |
1 |
|
|
T96 |
12 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1352 |
1 |
|
|
T96 |
37 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
644 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1281 |
1 |
|
|
T96 |
29 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
645 |
1 |
|
|
T96 |
12 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1319 |
1 |
|
|
T96 |
37 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
644 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1254 |
1 |
|
|
T96 |
27 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
645 |
1 |
|
|
T96 |
12 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1284 |
1 |
|
|
T96 |
36 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
643 |
1 |
|
|
T96 |
13 |
|
T97 |
17 |
|
T98 |
5 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1207 |
1 |
|
|
T96 |
26 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
645 |
1 |
|
|
T96 |
12 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1236 |
1 |
|
|
T96 |
35 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[0] |
auto[0] |
62954 |
1 |
|
|
T96 |
2058 |
|
T97 |
1646 |
|
T98 |
144 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[0] |
auto[1] |
42196 |
1 |
|
|
T96 |
711 |
|
T97 |
645 |
|
T98 |
176 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56858 |
1 |
|
|
T96 |
977 |
|
T97 |
830 |
|
T98 |
131 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[1] |
auto[1] |
42662 |
1 |
|
|
T96 |
801 |
|
T97 |
580 |
|
T98 |
763 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1584 |
1 |
|
|
T96 |
39 |
|
T97 |
36 |
|
T98 |
10 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1559 |
1 |
|
|
T96 |
39 |
|
T97 |
33 |
|
T98 |
9 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1559 |
1 |
|
|
T96 |
38 |
|
T97 |
34 |
|
T98 |
10 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1533 |
1 |
|
|
T96 |
39 |
|
T97 |
31 |
|
T98 |
9 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1517 |
1 |
|
|
T96 |
37 |
|
T97 |
32 |
|
T98 |
10 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1506 |
1 |
|
|
T96 |
38 |
|
T97 |
31 |
|
T98 |
9 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1493 |
1 |
|
|
T96 |
36 |
|
T97 |
32 |
|
T98 |
10 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1475 |
1 |
|
|
T96 |
38 |
|
T97 |
30 |
|
T98 |
7 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1453 |
1 |
|
|
T96 |
35 |
|
T97 |
32 |
|
T98 |
9 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1454 |
1 |
|
|
T96 |
37 |
|
T97 |
29 |
|
T98 |
7 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1420 |
1 |
|
|
T96 |
34 |
|
T97 |
31 |
|
T98 |
9 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T96 |
37 |
|
T97 |
29 |
|
T98 |
7 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1389 |
1 |
|
|
T96 |
33 |
|
T97 |
31 |
|
T98 |
9 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
714 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1394 |
1 |
|
|
T96 |
36 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1358 |
1 |
|
|
T96 |
32 |
|
T97 |
31 |
|
T98 |
9 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
714 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1355 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1328 |
1 |
|
|
T96 |
31 |
|
T97 |
31 |
|
T98 |
9 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1325 |
1 |
|
|
T96 |
35 |
|
T97 |
27 |
|
T98 |
6 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1288 |
1 |
|
|
T96 |
30 |
|
T97 |
31 |
|
T98 |
8 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1295 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
6 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T96 |
26 |
|
T97 |
29 |
|
T98 |
8 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1262 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
6 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1219 |
1 |
|
|
T96 |
24 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1238 |
1 |
|
|
T96 |
33 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1185 |
1 |
|
|
T96 |
21 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1213 |
1 |
|
|
T96 |
33 |
|
T97 |
23 |
|
T98 |
6 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1160 |
1 |
|
|
T96 |
21 |
|
T97 |
27 |
|
T98 |
8 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1184 |
1 |
|
|
T96 |
33 |
|
T97 |
22 |
|
T98 |
6 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1127 |
1 |
|
|
T96 |
21 |
|
T97 |
27 |
|
T98 |
7 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
18 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1145 |
1 |
|
|
T96 |
32 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53308 |
1 |
|
|
T96 |
1837 |
|
T97 |
693 |
|
T98 |
181 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47001 |
1 |
|
|
T96 |
825 |
|
T97 |
1444 |
|
T98 |
123 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56835 |
1 |
|
|
T96 |
1118 |
|
T97 |
691 |
|
T98 |
167 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46402 |
1 |
|
|
T96 |
708 |
|
T97 |
832 |
|
T98 |
778 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
18 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1640 |
1 |
|
|
T96 |
43 |
|
T97 |
40 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
741 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1596 |
1 |
|
|
T96 |
41 |
|
T97 |
41 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
18 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1612 |
1 |
|
|
T96 |
43 |
|
T97 |
39 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
741 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1564 |
1 |
|
|
T96 |
41 |
|
T97 |
40 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T96 |
18 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1581 |
1 |
|
|
T96 |
43 |
|
T97 |
39 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
740 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1524 |
1 |
|
|
T96 |
39 |
|
T97 |
40 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T96 |
18 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1538 |
1 |
|
|
T96 |
42 |
|
T97 |
37 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
740 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1491 |
1 |
|
|
T96 |
38 |
|
T97 |
39 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1494 |
1 |
|
|
T96 |
40 |
|
T97 |
36 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1462 |
1 |
|
|
T96 |
35 |
|
T97 |
39 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1465 |
1 |
|
|
T96 |
39 |
|
T97 |
35 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
736 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T96 |
35 |
|
T97 |
39 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1421 |
1 |
|
|
T96 |
35 |
|
T97 |
34 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1396 |
1 |
|
|
T96 |
35 |
|
T97 |
37 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1389 |
1 |
|
|
T96 |
35 |
|
T97 |
34 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1376 |
1 |
|
|
T96 |
35 |
|
T97 |
37 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1360 |
1 |
|
|
T96 |
34 |
|
T97 |
33 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
727 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1354 |
1 |
|
|
T96 |
34 |
|
T97 |
37 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1322 |
1 |
|
|
T96 |
34 |
|
T97 |
32 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
727 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1329 |
1 |
|
|
T96 |
34 |
|
T97 |
36 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1291 |
1 |
|
|
T96 |
33 |
|
T97 |
32 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1300 |
1 |
|
|
T96 |
33 |
|
T97 |
34 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1257 |
1 |
|
|
T96 |
30 |
|
T97 |
31 |
|
T98 |
7 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T96 |
19 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1272 |
1 |
|
|
T96 |
33 |
|
T97 |
34 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1229 |
1 |
|
|
T96 |
29 |
|
T97 |
31 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1241 |
1 |
|
|
T96 |
31 |
|
T97 |
34 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T96 |
28 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1215 |
1 |
|
|
T96 |
30 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T96 |
17 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1154 |
1 |
|
|
T96 |
28 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
724 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
4 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1186 |
1 |
|
|
T96 |
29 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57953 |
1 |
|
|
T96 |
1124 |
|
T97 |
869 |
|
T98 |
244 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45533 |
1 |
|
|
T96 |
1788 |
|
T97 |
1596 |
|
T98 |
81 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56672 |
1 |
|
|
T96 |
982 |
|
T97 |
781 |
|
T98 |
152 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43403 |
1 |
|
|
T96 |
695 |
|
T97 |
611 |
|
T98 |
752 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1617 |
1 |
|
|
T96 |
36 |
|
T97 |
34 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1632 |
1 |
|
|
T96 |
37 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1586 |
1 |
|
|
T96 |
36 |
|
T97 |
33 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1601 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T96 |
35 |
|
T97 |
33 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1579 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T96 |
35 |
|
T97 |
33 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1547 |
1 |
|
|
T96 |
34 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1487 |
1 |
|
|
T96 |
34 |
|
T97 |
32 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1518 |
1 |
|
|
T96 |
34 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1452 |
1 |
|
|
T96 |
33 |
|
T97 |
32 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1488 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
7 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1419 |
1 |
|
|
T96 |
33 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1452 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1385 |
1 |
|
|
T96 |
33 |
|
T97 |
29 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1425 |
1 |
|
|
T96 |
33 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1353 |
1 |
|
|
T96 |
32 |
|
T97 |
29 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1398 |
1 |
|
|
T96 |
33 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1326 |
1 |
|
|
T96 |
31 |
|
T97 |
29 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1369 |
1 |
|
|
T96 |
31 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1300 |
1 |
|
|
T96 |
31 |
|
T97 |
29 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1336 |
1 |
|
|
T96 |
30 |
|
T97 |
22 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1268 |
1 |
|
|
T96 |
30 |
|
T97 |
29 |
|
T98 |
5 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1304 |
1 |
|
|
T96 |
30 |
|
T97 |
21 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1236 |
1 |
|
|
T96 |
29 |
|
T97 |
29 |
|
T98 |
3 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1270 |
1 |
|
|
T96 |
29 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1201 |
1 |
|
|
T96 |
27 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1233 |
1 |
|
|
T96 |
28 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
19 |
|
T97 |
9 |
|
T98 |
6 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1162 |
1 |
|
|
T96 |
27 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1203 |
1 |
|
|
T96 |
25 |
|
T97 |
19 |
|
T98 |
6 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[0] |
auto[0] |
55815 |
1 |
|
|
T96 |
772 |
|
T97 |
1828 |
|
T98 |
182 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49157 |
1 |
|
|
T96 |
1015 |
|
T97 |
607 |
|
T98 |
139 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53544 |
1 |
|
|
T96 |
859 |
|
T97 |
754 |
|
T98 |
202 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44566 |
1 |
|
|
T96 |
1683 |
|
T97 |
623 |
|
T98 |
694 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1623 |
1 |
|
|
T96 |
48 |
|
T97 |
31 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1626 |
1 |
|
|
T96 |
48 |
|
T97 |
31 |
|
T98 |
8 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1591 |
1 |
|
|
T96 |
46 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1601 |
1 |
|
|
T96 |
46 |
|
T97 |
30 |
|
T98 |
8 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1555 |
1 |
|
|
T96 |
46 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1573 |
1 |
|
|
T96 |
46 |
|
T97 |
30 |
|
T98 |
8 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1525 |
1 |
|
|
T96 |
46 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1537 |
1 |
|
|
T96 |
45 |
|
T97 |
27 |
|
T98 |
7 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1506 |
1 |
|
|
T96 |
47 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1517 |
1 |
|
|
T96 |
44 |
|
T97 |
27 |
|
T98 |
7 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1474 |
1 |
|
|
T96 |
46 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1477 |
1 |
|
|
T96 |
44 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1453 |
1 |
|
|
T96 |
46 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1448 |
1 |
|
|
T96 |
42 |
|
T97 |
24 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1416 |
1 |
|
|
T96 |
45 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T96 |
17 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1408 |
1 |
|
|
T96 |
42 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1381 |
1 |
|
|
T96 |
43 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1373 |
1 |
|
|
T96 |
39 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1349 |
1 |
|
|
T96 |
43 |
|
T97 |
27 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1335 |
1 |
|
|
T96 |
37 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1311 |
1 |
|
|
T96 |
41 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1288 |
1 |
|
|
T96 |
36 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1291 |
1 |
|
|
T96 |
41 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1255 |
1 |
|
|
T96 |
36 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1260 |
1 |
|
|
T96 |
41 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1227 |
1 |
|
|
T96 |
36 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1232 |
1 |
|
|
T96 |
38 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1193 |
1 |
|
|
T96 |
35 |
|
T97 |
19 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T96 |
16 |
|
T97 |
15 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1195 |
1 |
|
|
T96 |
36 |
|
T97 |
24 |
|
T98 |
6 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
17 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1165 |
1 |
|
|
T96 |
34 |
|
T97 |
18 |
|
T98 |
4 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58072 |
1 |
|
|
T96 |
1855 |
|
T97 |
985 |
|
T98 |
923 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45101 |
1 |
|
|
T96 |
643 |
|
T97 |
1368 |
|
T98 |
156 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53897 |
1 |
|
|
T96 |
1161 |
|
T97 |
1306 |
|
T98 |
155 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46132 |
1 |
|
|
T96 |
1037 |
|
T97 |
335 |
|
T98 |
92 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1679 |
1 |
|
|
T96 |
31 |
|
T97 |
20 |
|
T98 |
5 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
658 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1683 |
1 |
|
|
T96 |
38 |
|
T97 |
19 |
|
T98 |
6 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1646 |
1 |
|
|
T96 |
30 |
|
T97 |
19 |
|
T98 |
5 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
658 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1651 |
1 |
|
|
T96 |
38 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1613 |
1 |
|
|
T96 |
29 |
|
T97 |
19 |
|
T98 |
5 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
658 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1620 |
1 |
|
|
T96 |
37 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T96 |
20 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1589 |
1 |
|
|
T96 |
29 |
|
T97 |
19 |
|
T98 |
5 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
658 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1597 |
1 |
|
|
T96 |
37 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
658 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1562 |
1 |
|
|
T96 |
30 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
656 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1577 |
1 |
|
|
T96 |
37 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
658 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T96 |
30 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
656 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1542 |
1 |
|
|
T96 |
37 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
654 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1483 |
1 |
|
|
T96 |
29 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
649 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1515 |
1 |
|
|
T96 |
35 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
654 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1446 |
1 |
|
|
T96 |
28 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
649 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1482 |
1 |
|
|
T96 |
34 |
|
T97 |
16 |
|
T98 |
5 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
652 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T96 |
28 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1448 |
1 |
|
|
T96 |
33 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
652 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1368 |
1 |
|
|
T96 |
27 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1412 |
1 |
|
|
T96 |
33 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
649 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1333 |
1 |
|
|
T96 |
27 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1379 |
1 |
|
|
T96 |
32 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
649 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1296 |
1 |
|
|
T96 |
25 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1352 |
1 |
|
|
T96 |
31 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
648 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1256 |
1 |
|
|
T96 |
25 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1313 |
1 |
|
|
T96 |
30 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
648 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1220 |
1 |
|
|
T96 |
24 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1279 |
1 |
|
|
T96 |
29 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
648 |
1 |
|
|
T96 |
19 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T96 |
24 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
12 |
|
T97 |
18 |
|
T98 |
2 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1249 |
1 |
|
|
T96 |
29 |
|
T97 |
14 |
|
T98 |
4 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[0] |
auto[0] |
54619 |
1 |
|
|
T96 |
1996 |
|
T97 |
1308 |
|
T98 |
103 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46202 |
1 |
|
|
T96 |
857 |
|
T97 |
686 |
|
T98 |
181 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[1] |
auto[0] |
50846 |
1 |
|
|
T96 |
737 |
|
T97 |
685 |
|
T98 |
820 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[1] |
auto[1] |
52054 |
1 |
|
|
T96 |
846 |
|
T97 |
1304 |
|
T98 |
153 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1624 |
1 |
|
|
T96 |
44 |
|
T97 |
24 |
|
T98 |
8 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1628 |
1 |
|
|
T96 |
50 |
|
T97 |
26 |
|
T98 |
8 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1583 |
1 |
|
|
T96 |
43 |
|
T97 |
22 |
|
T98 |
8 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1595 |
1 |
|
|
T96 |
50 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1550 |
1 |
|
|
T96 |
39 |
|
T97 |
22 |
|
T98 |
8 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1564 |
1 |
|
|
T96 |
49 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1525 |
1 |
|
|
T96 |
39 |
|
T97 |
21 |
|
T98 |
8 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1537 |
1 |
|
|
T96 |
48 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1489 |
1 |
|
|
T96 |
39 |
|
T97 |
19 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1506 |
1 |
|
|
T96 |
46 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1462 |
1 |
|
|
T96 |
39 |
|
T97 |
19 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1482 |
1 |
|
|
T96 |
45 |
|
T97 |
24 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1433 |
1 |
|
|
T96 |
39 |
|
T97 |
19 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1445 |
1 |
|
|
T96 |
44 |
|
T97 |
24 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1403 |
1 |
|
|
T96 |
39 |
|
T97 |
18 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1418 |
1 |
|
|
T96 |
43 |
|
T97 |
24 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
678 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1369 |
1 |
|
|
T96 |
37 |
|
T97 |
18 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1388 |
1 |
|
|
T96 |
41 |
|
T97 |
24 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
678 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1344 |
1 |
|
|
T96 |
36 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1361 |
1 |
|
|
T96 |
39 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1313 |
1 |
|
|
T96 |
35 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1329 |
1 |
|
|
T96 |
39 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1274 |
1 |
|
|
T96 |
35 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T96 |
12 |
|
T97 |
13 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1296 |
1 |
|
|
T96 |
39 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1233 |
1 |
|
|
T96 |
33 |
|
T97 |
18 |
|
T98 |
5 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
12 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1262 |
1 |
|
|
T96 |
37 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1207 |
1 |
|
|
T96 |
32 |
|
T97 |
18 |
|
T98 |
5 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
12 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1232 |
1 |
|
|
T96 |
36 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
2 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1180 |
1 |
|
|
T96 |
31 |
|
T97 |
18 |
|
T98 |
5 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
12 |
|
T97 |
12 |
|
T98 |
3 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1198 |
1 |
|
|
T96 |
35 |
|
T97 |
22 |
|
T98 |
7 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[0] |
auto[0] |
61438 |
1 |
|
|
T96 |
1481 |
|
T97 |
1566 |
|
T98 |
883 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44795 |
1 |
|
|
T96 |
787 |
|
T97 |
761 |
|
T98 |
117 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[1] |
auto[0] |
51248 |
1 |
|
|
T96 |
1775 |
|
T97 |
814 |
|
T98 |
218 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46377 |
1 |
|
|
T96 |
651 |
|
T97 |
649 |
|
T98 |
66 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
740 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1571 |
1 |
|
|
T96 |
31 |
|
T97 |
32 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1590 |
1 |
|
|
T96 |
34 |
|
T97 |
29 |
|
T98 |
5 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
740 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1535 |
1 |
|
|
T96 |
31 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1564 |
1 |
|
|
T96 |
34 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1505 |
1 |
|
|
T96 |
31 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1539 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
5 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T96 |
19 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1471 |
1 |
|
|
T96 |
31 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1521 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
5 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1436 |
1 |
|
|
T96 |
31 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
712 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1489 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
735 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1397 |
1 |
|
|
T96 |
30 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
712 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1462 |
1 |
|
|
T96 |
32 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1373 |
1 |
|
|
T96 |
29 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1437 |
1 |
|
|
T96 |
32 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1337 |
1 |
|
|
T96 |
29 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1414 |
1 |
|
|
T96 |
31 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1301 |
1 |
|
|
T96 |
28 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1383 |
1 |
|
|
T96 |
30 |
|
T97 |
25 |
|
T98 |
3 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1271 |
1 |
|
|
T96 |
26 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1353 |
1 |
|
|
T96 |
30 |
|
T97 |
24 |
|
T98 |
3 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1230 |
1 |
|
|
T96 |
24 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1319 |
1 |
|
|
T96 |
30 |
|
T97 |
24 |
|
T98 |
3 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1197 |
1 |
|
|
T96 |
24 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
16 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1293 |
1 |
|
|
T96 |
30 |
|
T97 |
24 |
|
T98 |
2 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1158 |
1 |
|
|
T96 |
24 |
|
T97 |
24 |
|
T98 |
3 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
700 |
1 |
|
|
T96 |
16 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1272 |
1 |
|
|
T96 |
28 |
|
T97 |
24 |
|
T98 |
2 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1121 |
1 |
|
|
T96 |
24 |
|
T97 |
22 |
|
T98 |
3 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
700 |
1 |
|
|
T96 |
16 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1242 |
1 |
|
|
T96 |
28 |
|
T97 |
22 |
|
T98 |
2 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
18 |
|
T97 |
14 |
|
T98 |
6 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1099 |
1 |
|
|
T96 |
24 |
|
T97 |
22 |
|
T98 |
3 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
700 |
1 |
|
|
T96 |
16 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1202 |
1 |
|
|
T96 |
28 |
|
T97 |
22 |
|
T98 |
2 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59984 |
1 |
|
|
T96 |
928 |
|
T97 |
747 |
|
T98 |
116 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44049 |
1 |
|
|
T96 |
742 |
|
T97 |
1483 |
|
T98 |
179 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53541 |
1 |
|
|
T96 |
1302 |
|
T97 |
909 |
|
T98 |
913 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45716 |
1 |
|
|
T96 |
1661 |
|
T97 |
615 |
|
T98 |
81 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
711 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1633 |
1 |
|
|
T96 |
43 |
|
T97 |
36 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1639 |
1 |
|
|
T96 |
41 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
711 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1606 |
1 |
|
|
T96 |
42 |
|
T97 |
35 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1610 |
1 |
|
|
T96 |
41 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1575 |
1 |
|
|
T96 |
39 |
|
T97 |
35 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1573 |
1 |
|
|
T96 |
41 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1541 |
1 |
|
|
T96 |
38 |
|
T97 |
35 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1536 |
1 |
|
|
T96 |
39 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1504 |
1 |
|
|
T96 |
36 |
|
T97 |
34 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
697 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1503 |
1 |
|
|
T96 |
36 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1466 |
1 |
|
|
T96 |
35 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
697 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1474 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1435 |
1 |
|
|
T96 |
35 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1446 |
1 |
|
|
T96 |
35 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1400 |
1 |
|
|
T96 |
32 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1418 |
1 |
|
|
T96 |
35 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T96 |
12 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1359 |
1 |
|
|
T96 |
32 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1378 |
1 |
|
|
T96 |
35 |
|
T97 |
24 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T96 |
12 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1324 |
1 |
|
|
T96 |
30 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1343 |
1 |
|
|
T96 |
35 |
|
T97 |
21 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
12 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1297 |
1 |
|
|
T96 |
29 |
|
T97 |
32 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1315 |
1 |
|
|
T96 |
34 |
|
T97 |
21 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
12 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1278 |
1 |
|
|
T96 |
29 |
|
T97 |
31 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1295 |
1 |
|
|
T96 |
33 |
|
T97 |
20 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
12 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1244 |
1 |
|
|
T96 |
29 |
|
T97 |
30 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1259 |
1 |
|
|
T96 |
33 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
12 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1218 |
1 |
|
|
T96 |
29 |
|
T97 |
30 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1237 |
1 |
|
|
T96 |
33 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T96 |
12 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1190 |
1 |
|
|
T96 |
29 |
|
T97 |
29 |
|
T98 |
6 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1199 |
1 |
|
|
T96 |
32 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59069 |
1 |
|
|
T96 |
1443 |
|
T97 |
708 |
|
T98 |
759 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45502 |
1 |
|
|
T96 |
667 |
|
T97 |
1337 |
|
T98 |
135 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55201 |
1 |
|
|
T96 |
2201 |
|
T97 |
985 |
|
T98 |
91 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44247 |
1 |
|
|
T96 |
470 |
|
T97 |
817 |
|
T98 |
223 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
711 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1603 |
1 |
|
|
T96 |
26 |
|
T97 |
35 |
|
T98 |
9 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
714 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1596 |
1 |
|
|
T96 |
29 |
|
T97 |
36 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
711 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1569 |
1 |
|
|
T96 |
26 |
|
T97 |
34 |
|
T98 |
9 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
714 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1561 |
1 |
|
|
T96 |
29 |
|
T97 |
34 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
711 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1539 |
1 |
|
|
T96 |
26 |
|
T97 |
33 |
|
T98 |
9 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
714 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1519 |
1 |
|
|
T96 |
27 |
|
T97 |
34 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
711 |
1 |
|
|
T96 |
21 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1504 |
1 |
|
|
T96 |
26 |
|
T97 |
30 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
714 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1489 |
1 |
|
|
T96 |
26 |
|
T97 |
34 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1478 |
1 |
|
|
T96 |
27 |
|
T97 |
29 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
710 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1467 |
1 |
|
|
T96 |
25 |
|
T97 |
33 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1450 |
1 |
|
|
T96 |
27 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
710 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1434 |
1 |
|
|
T96 |
24 |
|
T97 |
32 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T96 |
27 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1408 |
1 |
|
|
T96 |
23 |
|
T97 |
31 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1386 |
1 |
|
|
T96 |
26 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1373 |
1 |
|
|
T96 |
22 |
|
T97 |
30 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1353 |
1 |
|
|
T96 |
26 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1341 |
1 |
|
|
T96 |
22 |
|
T97 |
29 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1318 |
1 |
|
|
T96 |
26 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1315 |
1 |
|
|
T96 |
22 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1295 |
1 |
|
|
T96 |
25 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1283 |
1 |
|
|
T96 |
21 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1273 |
1 |
|
|
T96 |
25 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1247 |
1 |
|
|
T96 |
21 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1239 |
1 |
|
|
T96 |
25 |
|
T97 |
25 |
|
T98 |
5 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1204 |
1 |
|
|
T96 |
21 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1197 |
1 |
|
|
T96 |
24 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1184 |
1 |
|
|
T96 |
19 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
3 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1169 |
1 |
|
|
T96 |
24 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T96 |
18 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1159 |
1 |
|
|
T96 |
19 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58401 |
1 |
|
|
T96 |
1208 |
|
T97 |
593 |
|
T98 |
176 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48833 |
1 |
|
|
T96 |
801 |
|
T97 |
863 |
|
T98 |
122 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57212 |
1 |
|
|
T96 |
972 |
|
T97 |
1372 |
|
T98 |
126 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[1] |
auto[1] |
39737 |
1 |
|
|
T96 |
1558 |
|
T97 |
791 |
|
T98 |
858 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T96 |
22 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1571 |
1 |
|
|
T96 |
37 |
|
T97 |
43 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1571 |
1 |
|
|
T96 |
38 |
|
T97 |
41 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
738 |
1 |
|
|
T96 |
22 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1529 |
1 |
|
|
T96 |
36 |
|
T97 |
42 |
|
T98 |
5 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1535 |
1 |
|
|
T96 |
38 |
|
T97 |
41 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
737 |
1 |
|
|
T96 |
22 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1505 |
1 |
|
|
T96 |
35 |
|
T97 |
41 |
|
T98 |
5 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
730 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1500 |
1 |
|
|
T96 |
35 |
|
T97 |
41 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
737 |
1 |
|
|
T96 |
22 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1474 |
1 |
|
|
T96 |
33 |
|
T97 |
41 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
730 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1465 |
1 |
|
|
T96 |
33 |
|
T97 |
39 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T96 |
22 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1450 |
1 |
|
|
T96 |
33 |
|
T97 |
39 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1435 |
1 |
|
|
T96 |
33 |
|
T97 |
38 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T96 |
22 |
|
T97 |
10 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1424 |
1 |
|
|
T96 |
31 |
|
T97 |
39 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
726 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1399 |
1 |
|
|
T96 |
32 |
|
T97 |
36 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T96 |
22 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1398 |
1 |
|
|
T96 |
30 |
|
T97 |
36 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1369 |
1 |
|
|
T96 |
31 |
|
T97 |
36 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
728 |
1 |
|
|
T96 |
22 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1362 |
1 |
|
|
T96 |
29 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1339 |
1 |
|
|
T96 |
31 |
|
T97 |
35 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
21 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1334 |
1 |
|
|
T96 |
27 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1309 |
1 |
|
|
T96 |
31 |
|
T97 |
34 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
21 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1298 |
1 |
|
|
T96 |
25 |
|
T97 |
32 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1278 |
1 |
|
|
T96 |
31 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
21 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1276 |
1 |
|
|
T96 |
25 |
|
T97 |
32 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1249 |
1 |
|
|
T96 |
31 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T96 |
21 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1245 |
1 |
|
|
T96 |
24 |
|
T97 |
32 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1219 |
1 |
|
|
T96 |
31 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T96 |
21 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1214 |
1 |
|
|
T96 |
23 |
|
T97 |
32 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1188 |
1 |
|
|
T96 |
29 |
|
T97 |
33 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T96 |
21 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1189 |
1 |
|
|
T96 |
23 |
|
T97 |
32 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1159 |
1 |
|
|
T96 |
28 |
|
T97 |
32 |
|
T98 |
6 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T96 |
21 |
|
T97 |
10 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1159 |
1 |
|
|
T96 |
23 |
|
T97 |
31 |
|
T98 |
3 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T96 |
21 |
|
T97 |
13 |
|
T98 |
4 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1124 |
1 |
|
|
T96 |
28 |
|
T97 |
31 |
|
T98 |
6 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58752 |
1 |
|
|
T96 |
1021 |
|
T97 |
882 |
|
T98 |
787 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49918 |
1 |
|
|
T96 |
843 |
|
T97 |
1371 |
|
T98 |
195 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[1] |
auto[0] |
50045 |
1 |
|
|
T96 |
1101 |
|
T97 |
762 |
|
T98 |
183 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45171 |
1 |
|
|
T96 |
1580 |
|
T97 |
754 |
|
T98 |
124 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T96 |
15 |
|
T97 |
11 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1643 |
1 |
|
|
T96 |
41 |
|
T97 |
35 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
15 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1642 |
1 |
|
|
T96 |
41 |
|
T97 |
28 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T96 |
15 |
|
T97 |
11 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1608 |
1 |
|
|
T96 |
41 |
|
T97 |
35 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
15 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1599 |
1 |
|
|
T96 |
41 |
|
T97 |
27 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
15 |
|
T97 |
11 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1569 |
1 |
|
|
T96 |
41 |
|
T97 |
34 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
15 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1562 |
1 |
|
|
T96 |
41 |
|
T97 |
27 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T96 |
15 |
|
T97 |
11 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1530 |
1 |
|
|
T96 |
41 |
|
T97 |
34 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
15 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1527 |
1 |
|
|
T96 |
39 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1496 |
1 |
|
|
T96 |
41 |
|
T97 |
34 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T96 |
15 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1486 |
1 |
|
|
T96 |
39 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1470 |
1 |
|
|
T96 |
40 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T96 |
15 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1460 |
1 |
|
|
T96 |
38 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1432 |
1 |
|
|
T96 |
39 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
15 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1424 |
1 |
|
|
T96 |
36 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T96 |
37 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
15 |
|
T97 |
18 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1390 |
1 |
|
|
T96 |
35 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1394 |
1 |
|
|
T96 |
37 |
|
T97 |
33 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1337 |
1 |
|
|
T96 |
34 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1362 |
1 |
|
|
T96 |
36 |
|
T97 |
32 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1313 |
1 |
|
|
T96 |
34 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1327 |
1 |
|
|
T96 |
36 |
|
T97 |
31 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1280 |
1 |
|
|
T96 |
34 |
|
T97 |
23 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1294 |
1 |
|
|
T96 |
36 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1246 |
1 |
|
|
T96 |
33 |
|
T97 |
23 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1265 |
1 |
|
|
T96 |
34 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1215 |
1 |
|
|
T96 |
33 |
|
T97 |
22 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1242 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1187 |
1 |
|
|
T96 |
32 |
|
T97 |
21 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T96 |
14 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1215 |
1 |
|
|
T96 |
32 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1158 |
1 |
|
|
T96 |
32 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56239 |
1 |
|
|
T96 |
972 |
|
T97 |
1674 |
|
T98 |
119 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49835 |
1 |
|
|
T96 |
1746 |
|
T97 |
527 |
|
T98 |
134 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[1] |
auto[0] |
51068 |
1 |
|
|
T96 |
1204 |
|
T97 |
983 |
|
T98 |
777 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45198 |
1 |
|
|
T96 |
768 |
|
T97 |
592 |
|
T98 |
165 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
628 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1753 |
1 |
|
|
T96 |
35 |
|
T97 |
30 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
658 |
1 |
|
|
T96 |
19 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1718 |
1 |
|
|
T96 |
30 |
|
T97 |
31 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
628 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1714 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
658 |
1 |
|
|
T96 |
19 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1688 |
1 |
|
|
T96 |
30 |
|
T97 |
30 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
628 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1681 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T96 |
19 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1661 |
1 |
|
|
T96 |
30 |
|
T97 |
29 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
628 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1644 |
1 |
|
|
T96 |
35 |
|
T97 |
28 |
|
T98 |
8 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T96 |
19 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1633 |
1 |
|
|
T96 |
30 |
|
T97 |
27 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
624 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1611 |
1 |
|
|
T96 |
32 |
|
T97 |
27 |
|
T98 |
8 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
652 |
1 |
|
|
T96 |
19 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1606 |
1 |
|
|
T96 |
29 |
|
T97 |
27 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
624 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1580 |
1 |
|
|
T96 |
32 |
|
T97 |
27 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
652 |
1 |
|
|
T96 |
19 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1578 |
1 |
|
|
T96 |
29 |
|
T97 |
26 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
619 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1547 |
1 |
|
|
T96 |
32 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
649 |
1 |
|
|
T96 |
19 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1552 |
1 |
|
|
T96 |
29 |
|
T97 |
26 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
619 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1512 |
1 |
|
|
T96 |
32 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
649 |
1 |
|
|
T96 |
19 |
|
T97 |
16 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1522 |
1 |
|
|
T96 |
28 |
|
T97 |
26 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
615 |
1 |
|
|
T96 |
14 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1474 |
1 |
|
|
T96 |
32 |
|
T97 |
25 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
646 |
1 |
|
|
T96 |
19 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1484 |
1 |
|
|
T96 |
28 |
|
T97 |
27 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
615 |
1 |
|
|
T96 |
14 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1433 |
1 |
|
|
T96 |
31 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
646 |
1 |
|
|
T96 |
19 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1433 |
1 |
|
|
T96 |
27 |
|
T97 |
27 |
|
T98 |
9 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
613 |
1 |
|
|
T96 |
14 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1400 |
1 |
|
|
T96 |
31 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
19 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1398 |
1 |
|
|
T96 |
27 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
613 |
1 |
|
|
T96 |
14 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1364 |
1 |
|
|
T96 |
31 |
|
T97 |
22 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
19 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1367 |
1 |
|
|
T96 |
27 |
|
T97 |
26 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
612 |
1 |
|
|
T96 |
14 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1325 |
1 |
|
|
T96 |
30 |
|
T97 |
20 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
19 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1335 |
1 |
|
|
T96 |
25 |
|
T97 |
25 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
612 |
1 |
|
|
T96 |
14 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1286 |
1 |
|
|
T96 |
30 |
|
T97 |
20 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
19 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1304 |
1 |
|
|
T96 |
24 |
|
T97 |
25 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
611 |
1 |
|
|
T96 |
14 |
|
T97 |
17 |
|
T98 |
3 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1260 |
1 |
|
|
T96 |
29 |
|
T97 |
19 |
|
T98 |
7 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
644 |
1 |
|
|
T96 |
19 |
|
T97 |
15 |
|
T98 |
4 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1264 |
1 |
|
|
T96 |
23 |
|
T97 |
24 |
|
T98 |
7 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[0] |
auto[0] |
55610 |
1 |
|
|
T96 |
917 |
|
T97 |
1676 |
|
T98 |
177 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[0] |
auto[1] |
43752 |
1 |
|
|
T96 |
841 |
|
T97 |
633 |
|
T98 |
98 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57292 |
1 |
|
|
T96 |
1315 |
|
T97 |
950 |
|
T98 |
971 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[1] |
auto[1] |
47702 |
1 |
|
|
T96 |
1594 |
|
T97 |
647 |
|
T98 |
49 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
6 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1576 |
1 |
|
|
T96 |
37 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
18 |
|
T97 |
13 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1589 |
1 |
|
|
T96 |
35 |
|
T97 |
27 |
|
T98 |
2 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
725 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
6 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1539 |
1 |
|
|
T96 |
36 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
18 |
|
T97 |
13 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1542 |
1 |
|
|
T96 |
34 |
|
T97 |
26 |
|
T98 |
2 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
6 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1507 |
1 |
|
|
T96 |
36 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
18 |
|
T97 |
13 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1513 |
1 |
|
|
T96 |
33 |
|
T97 |
26 |
|
T98 |
2 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
724 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
6 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1479 |
1 |
|
|
T96 |
35 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T96 |
18 |
|
T97 |
13 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1479 |
1 |
|
|
T96 |
33 |
|
T97 |
26 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
6 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1445 |
1 |
|
|
T96 |
35 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
712 |
1 |
|
|
T96 |
18 |
|
T97 |
13 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1457 |
1 |
|
|
T96 |
33 |
|
T97 |
26 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
6 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1403 |
1 |
|
|
T96 |
33 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
712 |
1 |
|
|
T96 |
18 |
|
T97 |
13 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1435 |
1 |
|
|
T96 |
33 |
|
T97 |
25 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1372 |
1 |
|
|
T96 |
32 |
|
T97 |
27 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
708 |
1 |
|
|
T96 |
18 |
|
T97 |
13 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1401 |
1 |
|
|
T96 |
31 |
|
T97 |
23 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1342 |
1 |
|
|
T96 |
30 |
|
T97 |
26 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
708 |
1 |
|
|
T96 |
18 |
|
T97 |
13 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1368 |
1 |
|
|
T96 |
31 |
|
T97 |
23 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1314 |
1 |
|
|
T96 |
30 |
|
T97 |
26 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T96 |
18 |
|
T97 |
12 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1341 |
1 |
|
|
T96 |
31 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1278 |
1 |
|
|
T96 |
28 |
|
T97 |
26 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T96 |
18 |
|
T97 |
12 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1315 |
1 |
|
|
T96 |
31 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
711 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1243 |
1 |
|
|
T96 |
27 |
|
T97 |
24 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T96 |
18 |
|
T97 |
12 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1283 |
1 |
|
|
T96 |
30 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
711 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1206 |
1 |
|
|
T96 |
26 |
|
T97 |
23 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T96 |
18 |
|
T97 |
12 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1260 |
1 |
|
|
T96 |
28 |
|
T97 |
24 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1175 |
1 |
|
|
T96 |
25 |
|
T97 |
23 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
18 |
|
T97 |
12 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1241 |
1 |
|
|
T96 |
28 |
|
T97 |
23 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1143 |
1 |
|
|
T96 |
24 |
|
T97 |
23 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
18 |
|
T97 |
12 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1213 |
1 |
|
|
T96 |
27 |
|
T97 |
23 |
|
T98 |
1 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
15 |
|
T97 |
13 |
|
T98 |
5 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1110 |
1 |
|
|
T96 |
23 |
|
T97 |
22 |
|
T98 |
3 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
18 |
|
T97 |
12 |
|
T98 |
7 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1187 |
1 |
|
|
T96 |
26 |
|
T97 |
23 |
|
T98 |
1 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[0] |
auto[0] |
52664 |
1 |
|
|
T96 |
1027 |
|
T97 |
759 |
|
T98 |
149 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45584 |
1 |
|
|
T96 |
860 |
|
T97 |
796 |
|
T98 |
767 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53412 |
1 |
|
|
T96 |
1171 |
|
T97 |
1334 |
|
T98 |
176 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[1] |
auto[1] |
51752 |
1 |
|
|
T96 |
1557 |
|
T97 |
1045 |
|
T98 |
152 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1661 |
1 |
|
|
T96 |
39 |
|
T97 |
32 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1637 |
1 |
|
|
T96 |
43 |
|
T97 |
29 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1631 |
1 |
|
|
T96 |
38 |
|
T97 |
32 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1615 |
1 |
|
|
T96 |
42 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
669 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1593 |
1 |
|
|
T96 |
37 |
|
T97 |
32 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1586 |
1 |
|
|
T96 |
42 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
669 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1556 |
1 |
|
|
T96 |
36 |
|
T97 |
32 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1557 |
1 |
|
|
T96 |
41 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1524 |
1 |
|
|
T96 |
35 |
|
T97 |
31 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1527 |
1 |
|
|
T96 |
41 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1489 |
1 |
|
|
T96 |
32 |
|
T97 |
30 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1492 |
1 |
|
|
T96 |
41 |
|
T97 |
26 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
661 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1455 |
1 |
|
|
T96 |
32 |
|
T97 |
30 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1462 |
1 |
|
|
T96 |
41 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
661 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1414 |
1 |
|
|
T96 |
31 |
|
T97 |
29 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T96 |
13 |
|
T97 |
12 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1434 |
1 |
|
|
T96 |
40 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
655 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1377 |
1 |
|
|
T96 |
31 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1407 |
1 |
|
|
T96 |
36 |
|
T97 |
25 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
655 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1345 |
1 |
|
|
T96 |
30 |
|
T97 |
28 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1381 |
1 |
|
|
T96 |
35 |
|
T97 |
25 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
653 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1312 |
1 |
|
|
T96 |
28 |
|
T97 |
25 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1360 |
1 |
|
|
T96 |
34 |
|
T97 |
25 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
653 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1275 |
1 |
|
|
T96 |
24 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1332 |
1 |
|
|
T96 |
33 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
653 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1244 |
1 |
|
|
T96 |
23 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1300 |
1 |
|
|
T96 |
32 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
653 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1221 |
1 |
|
|
T96 |
23 |
|
T97 |
23 |
|
T98 |
7 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1269 |
1 |
|
|
T96 |
32 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
653 |
1 |
|
|
T96 |
17 |
|
T97 |
8 |
|
T98 |
3 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1195 |
1 |
|
|
T96 |
22 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T96 |
13 |
|
T97 |
11 |
|
T98 |
5 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1234 |
1 |
|
|
T96 |
32 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[0] |
auto[0] |
55269 |
1 |
|
|
T96 |
1215 |
|
T97 |
1030 |
|
T98 |
287 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[0] |
auto[1] |
43777 |
1 |
|
|
T96 |
1534 |
|
T97 |
803 |
|
T98 |
78 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[1] |
auto[0] |
52703 |
1 |
|
|
T96 |
1165 |
|
T97 |
693 |
|
T98 |
847 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[1] |
auto[1] |
50701 |
1 |
|
|
T96 |
675 |
|
T97 |
1357 |
|
T98 |
11 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1646 |
1 |
|
|
T96 |
32 |
|
T97 |
32 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
730 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1633 |
1 |
|
|
T96 |
35 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1611 |
1 |
|
|
T96 |
30 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
730 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1607 |
1 |
|
|
T96 |
34 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1587 |
1 |
|
|
T96 |
30 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1581 |
1 |
|
|
T96 |
32 |
|
T97 |
32 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1559 |
1 |
|
|
T96 |
30 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
729 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1550 |
1 |
|
|
T96 |
32 |
|
T97 |
30 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T96 |
30 |
|
T97 |
30 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1514 |
1 |
|
|
T96 |
31 |
|
T97 |
29 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1490 |
1 |
|
|
T96 |
29 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
725 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1475 |
1 |
|
|
T96 |
30 |
|
T97 |
26 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1448 |
1 |
|
|
T96 |
29 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1450 |
1 |
|
|
T96 |
29 |
|
T97 |
26 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1417 |
1 |
|
|
T96 |
26 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1416 |
1 |
|
|
T96 |
29 |
|
T97 |
25 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
704 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1385 |
1 |
|
|
T96 |
25 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1391 |
1 |
|
|
T96 |
29 |
|
T97 |
24 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
704 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1357 |
1 |
|
|
T96 |
25 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1357 |
1 |
|
|
T96 |
29 |
|
T97 |
23 |
|
T98 |
2 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1328 |
1 |
|
|
T96 |
24 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1328 |
1 |
|
|
T96 |
28 |
|
T97 |
23 |
|
T98 |
1 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1295 |
1 |
|
|
T96 |
24 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T96 |
20 |
|
T97 |
12 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1299 |
1 |
|
|
T96 |
27 |
|
T97 |
23 |
|
T99 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1260 |
1 |
|
|
T96 |
23 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1259 |
1 |
|
|
T96 |
26 |
|
T97 |
22 |
|
T99 |
6 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1228 |
1 |
|
|
T96 |
23 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1228 |
1 |
|
|
T96 |
26 |
|
T97 |
21 |
|
T99 |
6 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T96 |
24 |
|
T97 |
11 |
|
T98 |
7 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T96 |
23 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T96 |
20 |
|
T97 |
11 |
|
T98 |
9 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1181 |
1 |
|
|
T96 |
22 |
|
T97 |
21 |
|
T99 |
6 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[0] |
auto[0] |
51627 |
1 |
|
|
T96 |
1201 |
|
T97 |
868 |
|
T98 |
671 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49492 |
1 |
|
|
T96 |
664 |
|
T97 |
1374 |
|
T98 |
90 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57936 |
1 |
|
|
T96 |
1213 |
|
T97 |
1120 |
|
T98 |
293 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43986 |
1 |
|
|
T96 |
1573 |
|
T97 |
560 |
|
T98 |
315 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
655 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1688 |
1 |
|
|
T96 |
37 |
|
T97 |
30 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T96 |
16 |
|
T97 |
14 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1675 |
1 |
|
|
T96 |
37 |
|
T97 |
28 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
655 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1652 |
1 |
|
|
T96 |
37 |
|
T97 |
29 |
|
T98 |
4 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T96 |
16 |
|
T97 |
14 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1640 |
1 |
|
|
T96 |
37 |
|
T97 |
27 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
654 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1621 |
1 |
|
|
T96 |
36 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T96 |
16 |
|
T97 |
14 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1602 |
1 |
|
|
T96 |
37 |
|
T97 |
26 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
654 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1591 |
1 |
|
|
T96 |
36 |
|
T97 |
28 |
|
T98 |
4 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T96 |
16 |
|
T97 |
14 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1570 |
1 |
|
|
T96 |
35 |
|
T97 |
26 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
652 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1563 |
1 |
|
|
T96 |
36 |
|
T97 |
27 |
|
T98 |
4 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
665 |
1 |
|
|
T96 |
16 |
|
T97 |
14 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1540 |
1 |
|
|
T96 |
34 |
|
T97 |
26 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
652 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1541 |
1 |
|
|
T96 |
35 |
|
T97 |
26 |
|
T98 |
4 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
665 |
1 |
|
|
T96 |
16 |
|
T97 |
14 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1503 |
1 |
|
|
T96 |
32 |
|
T97 |
25 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
647 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1513 |
1 |
|
|
T96 |
34 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
663 |
1 |
|
|
T96 |
16 |
|
T97 |
14 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1470 |
1 |
|
|
T96 |
32 |
|
T97 |
25 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
647 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1485 |
1 |
|
|
T96 |
32 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
663 |
1 |
|
|
T96 |
16 |
|
T97 |
14 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1438 |
1 |
|
|
T96 |
32 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
640 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1456 |
1 |
|
|
T96 |
31 |
|
T97 |
25 |
|
T98 |
4 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1406 |
1 |
|
|
T96 |
31 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
640 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1428 |
1 |
|
|
T96 |
30 |
|
T97 |
23 |
|
T98 |
3 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1373 |
1 |
|
|
T96 |
31 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
638 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1393 |
1 |
|
|
T96 |
30 |
|
T97 |
21 |
|
T98 |
3 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1350 |
1 |
|
|
T96 |
31 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
638 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1362 |
1 |
|
|
T96 |
30 |
|
T97 |
21 |
|
T98 |
3 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1324 |
1 |
|
|
T96 |
29 |
|
T97 |
23 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
638 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1318 |
1 |
|
|
T96 |
28 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
659 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1302 |
1 |
|
|
T96 |
27 |
|
T97 |
22 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
638 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1280 |
1 |
|
|
T96 |
28 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
659 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1267 |
1 |
|
|
T96 |
24 |
|
T97 |
22 |
|
T98 |
5 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
638 |
1 |
|
|
T96 |
16 |
|
T97 |
12 |
|
T98 |
2 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T96 |
27 |
|
T97 |
19 |
|
T98 |
3 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
659 |
1 |
|
|
T96 |
16 |
|
T97 |
13 |
|
T98 |
1 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1233 |
1 |
|
|
T96 |
24 |
|
T97 |
22 |
|
T98 |
5 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58758 |
1 |
|
|
T96 |
1011 |
|
T97 |
1597 |
|
T98 |
162 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47905 |
1 |
|
|
T96 |
1553 |
|
T97 |
541 |
|
T98 |
785 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55769 |
1 |
|
|
T96 |
938 |
|
T97 |
1223 |
|
T98 |
151 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[1] |
auto[1] |
41187 |
1 |
|
|
T96 |
931 |
|
T97 |
544 |
|
T98 |
96 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1591 |
1 |
|
|
T96 |
47 |
|
T97 |
26 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1596 |
1 |
|
|
T96 |
46 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1554 |
1 |
|
|
T96 |
45 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1572 |
1 |
|
|
T96 |
46 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1530 |
1 |
|
|
T96 |
43 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1538 |
1 |
|
|
T96 |
46 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1514 |
1 |
|
|
T96 |
43 |
|
T97 |
24 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1513 |
1 |
|
|
T96 |
46 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1487 |
1 |
|
|
T96 |
44 |
|
T97 |
22 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1486 |
1 |
|
|
T96 |
45 |
|
T97 |
25 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
7 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1459 |
1 |
|
|
T96 |
44 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1460 |
1 |
|
|
T96 |
44 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1427 |
1 |
|
|
T96 |
42 |
|
T97 |
20 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1431 |
1 |
|
|
T96 |
44 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
709 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1392 |
1 |
|
|
T96 |
37 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T96 |
15 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1397 |
1 |
|
|
T96 |
44 |
|
T97 |
24 |
|
T98 |
5 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
704 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1369 |
1 |
|
|
T96 |
35 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1366 |
1 |
|
|
T96 |
43 |
|
T97 |
25 |
|
T98 |
5 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
704 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1341 |
1 |
|
|
T96 |
34 |
|
T97 |
18 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1329 |
1 |
|
|
T96 |
42 |
|
T97 |
23 |
|
T98 |
4 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1316 |
1 |
|
|
T96 |
34 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1289 |
1 |
|
|
T96 |
42 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1290 |
1 |
|
|
T96 |
33 |
|
T97 |
17 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1262 |
1 |
|
|
T96 |
42 |
|
T97 |
21 |
|
T98 |
4 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1254 |
1 |
|
|
T96 |
32 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1224 |
1 |
|
|
T96 |
41 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1220 |
1 |
|
|
T96 |
30 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1199 |
1 |
|
|
T96 |
39 |
|
T97 |
20 |
|
T98 |
4 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T96 |
14 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T96 |
27 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T96 |
15 |
|
T97 |
16 |
|
T98 |
6 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1175 |
1 |
|
|
T96 |
39 |
|
T97 |
20 |
|
T98 |
4 |