Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4182358	1			T23	31		T24	58		T25	32970
all_pins[1]	4182358	1			T23	31		T24	58		T25	32970
all_pins[2]	4182358	1			T23	31		T24	58		T25	32970
all_pins[3]	4182358	1			T23	31		T24	58		T25	32970
all_pins[4]	4182358	1			T23	31		T24	58		T25	32970
all_pins[5]	4182358	1			T23	31		T24	58		T25	32970
all_pins[6]	4182358	1			T23	31		T24	58		T25	32970
all_pins[7]	4182358	1			T23	31		T24	58		T25	32970
all_pins[8]	4182358	1			T23	31		T24	58		T25	32970
all_pins[9]	4182358	1			T23	31		T24	58		T25	32970
all_pins[10]	4182358	1			T23	31		T24	58		T25	32970
all_pins[11]	4182358	1			T23	31		T24	58		T25	32970
all_pins[12]	4182358	1			T23	31		T24	58		T25	32970
all_pins[13]	4182358	1			T23	31		T24	58		T25	32970
all_pins[14]	4182358	1			T23	31		T24	58		T25	32970
all_pins[15]	4182358	1			T23	31		T24	58		T25	32970
all_pins[16]	4182358	1			T23	31		T24	58		T25	32970
all_pins[17]	4182358	1			T23	31		T24	58		T25	32970
all_pins[18]	4182358	1			T23	31		T24	58		T25	32970
all_pins[19]	4182358	1			T23	31		T24	58		T25	32970
all_pins[20]	4182358	1			T23	31		T24	58		T25	32970
all_pins[21]	4182358	1			T23	31		T24	58		T25	32970
all_pins[22]	4182358	1			T23	31		T24	58		T25	32970
all_pins[23]	4182358	1			T23	31		T24	58		T25	32970
all_pins[24]	4182358	1			T23	31		T24	58		T25	32970
all_pins[25]	4182358	1			T23	31		T24	58		T25	32970
all_pins[26]	4182358	1			T23	31		T24	58		T25	32970
all_pins[27]	4182358	1			T23	31		T24	58		T25	32970
all_pins[28]	4182358	1			T23	31		T24	58		T25	32970
all_pins[29]	4182358	1			T23	31		T24	58		T25	32970
all_pins[30]	4182358	1			T23	31		T24	58		T25	32970
all_pins[31]	4182358	1			T23	31		T24	58		T25	32970

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	83178483	1			T23	992		T24	1611		T25	657628
values[0x1]	50656973	1			T24	245		T25	397412		T26	13983
transitions[0x0=>0x1]	30371604	1			T24	162		T25	238198		T26	8290
transitions[0x1=>0x0]	30371437	1			T24	162		T25	238198		T26	8290

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2609166	1			T23	31		T24	57		T25	20872
all_pins[0]	values[0x1]	1573192	1			T24	1		T25	12098		T26	454
all_pins[0]	transitions[0x0=>0x1]	975421	1			T24	1		T25	7598		T26	280
all_pins[0]	transitions[0x1=>0x0]	987723	1			T24	11		T25	7539		T26	243
all_pins[1]	values[0x0]	2602127	1			T23	31		T24	43		T25	20634
all_pins[1]	values[0x1]	1580231	1			T24	15		T25	12336		T26	396
all_pins[1]	transitions[0x0=>0x1]	949396	1			T24	15		T25	7522		T26	230
all_pins[1]	transitions[0x1=>0x0]	942357	1			T24	1		T25	7284		T26	288
all_pins[2]	values[0x0]	2600627	1			T23	31		T24	53		T25	20608
all_pins[2]	values[0x1]	1581731	1			T24	5		T25	12362		T26	356
all_pins[2]	transitions[0x0=>0x1]	949436	1			T24	1		T25	7383		T26	200
all_pins[2]	transitions[0x1=>0x0]	947936	1			T24	11		T25	7357		T26	240
all_pins[3]	values[0x0]	2598372	1			T23	31		T24	50		T25	20876
all_pins[3]	values[0x1]	1583986	1			T24	8		T25	12094		T26	479
all_pins[3]	transitions[0x0=>0x1]	950618	1			T24	8		T25	7151		T26	333
all_pins[3]	transitions[0x1=>0x0]	948363	1			T24	5		T25	7419		T26	210
all_pins[4]	values[0x0]	2596578	1			T23	31		T24	44		T25	20389
all_pins[4]	values[0x1]	1585780	1			T24	14		T25	12581		T26	413
all_pins[4]	transitions[0x0=>0x1]	949504	1			T24	8		T25	7833		T26	235
all_pins[4]	transitions[0x1=>0x0]	947710	1			T24	2		T25	7346		T26	301
all_pins[5]	values[0x0]	2598263	1			T23	31		T24	50		T25	20232
all_pins[5]	values[0x1]	1584095	1			T24	8		T25	12738		T26	378
all_pins[5]	transitions[0x0=>0x1]	947031	1			T24	1		T25	7849		T26	220
all_pins[5]	transitions[0x1=>0x0]	948716	1			T24	7		T25	7692		T26	255
all_pins[6]	values[0x0]	2597137	1			T23	31		T24	50		T25	20559
all_pins[6]	values[0x1]	1585221	1			T24	8		T25	12411		T26	484
all_pins[6]	transitions[0x0=>0x1]	951556	1			T25	7295		T26	310		T29	19825
all_pins[6]	transitions[0x1=>0x0]	950430	1			T25	7622		T26	204		T29	19318
all_pins[7]	values[0x0]	2598873	1			T23	31		T24	54		T25	20462
all_pins[7]	values[0x1]	1583485	1			T24	4		T25	12508		T26	506
all_pins[7]	transitions[0x0=>0x1]	946498	1			T24	4		T25	7587		T26	286
all_pins[7]	transitions[0x1=>0x0]	948234	1			T24	8		T25	7490		T26	264
all_pins[8]	values[0x0]	2600678	1			T23	31		T24	51		T25	21043
all_pins[8]	values[0x1]	1581680	1			T24	7		T25	11927		T26	455
all_pins[8]	transitions[0x0=>0x1]	945852	1			T24	7		T25	7062		T26	208
all_pins[8]	transitions[0x1=>0x0]	947657	1			T24	4		T25	7643		T26	259
all_pins[9]	values[0x0]	2602937	1			T23	31		T24	46		T25	20121
all_pins[9]	values[0x1]	1579421	1			T24	12		T25	12849		T26	434
all_pins[9]	transitions[0x0=>0x1]	945742	1			T24	8		T25	7924		T26	224
all_pins[9]	transitions[0x1=>0x0]	948001	1			T24	3		T25	7002		T26	245
all_pins[10]	values[0x0]	2602863	1			T23	31		T24	52		T25	20127
all_pins[10]	values[0x1]	1579495	1			T24	6		T25	12843		T26	481
all_pins[10]	transitions[0x0=>0x1]	947198	1			T24	1		T25	7507		T26	289
all_pins[10]	transitions[0x1=>0x0]	947124	1			T24	7		T25	7513		T26	242
all_pins[11]	values[0x0]	2595563	1			T23	31		T24	54		T25	20460
all_pins[11]	values[0x1]	1586795	1			T24	4		T25	12510		T26	411
all_pins[11]	transitions[0x0=>0x1]	951226	1			T24	1		T25	7307		T26	238
all_pins[11]	transitions[0x1=>0x0]	943926	1			T24	3		T25	7640		T26	308
all_pins[12]	values[0x0]	2596894	1			T23	31		T24	47		T25	20778
all_pins[12]	values[0x1]	1585464	1			T24	11		T25	12192		T26	510
all_pins[12]	transitions[0x0=>0x1]	948338	1			T24	10		T25	7324		T26	293
all_pins[12]	transitions[0x1=>0x0]	949669	1			T24	3		T25	7642		T26	194
all_pins[13]	values[0x0]	2594465	1			T23	31		T24	49		T25	20388
all_pins[13]	values[0x1]	1587893	1			T24	9		T25	12582		T26	467
all_pins[13]	transitions[0x0=>0x1]	948578	1			T24	6		T25	7636		T26	237
all_pins[13]	transitions[0x1=>0x0]	946149	1			T24	8		T25	7246		T26	280
all_pins[14]	values[0x0]	2604967	1			T23	31		T24	50		T25	20468
all_pins[14]	values[0x1]	1577391	1			T24	8		T25	12502		T26	391
all_pins[14]	transitions[0x0=>0x1]	941928	1			T24	5		T25	7342		T26	220
all_pins[14]	transitions[0x1=>0x0]	952430	1			T24	6		T25	7422		T26	296
all_pins[15]	values[0x0]	2595674	1			T23	31		T24	44		T25	20686
all_pins[15]	values[0x1]	1586684	1			T24	14		T25	12284		T26	487
all_pins[15]	transitions[0x0=>0x1]	953072	1			T24	10		T25	7309		T26	297
all_pins[15]	transitions[0x1=>0x0]	943779	1			T24	4		T25	7527		T26	201
all_pins[16]	values[0x0]	2602045	1			T23	31		T24	53		T25	20587
all_pins[16]	values[0x1]	1580313	1			T24	5		T25	12383		T26	409
all_pins[16]	transitions[0x0=>0x1]	944288	1			T24	5		T25	7517		T26	204
all_pins[16]	transitions[0x1=>0x0]	950659	1			T24	14		T25	7418		T26	282
all_pins[17]	values[0x0]	2591333	1			T23	31		T24	46		T25	20544
all_pins[17]	values[0x1]	1591025	1			T24	12		T25	12426		T26	395
all_pins[17]	transitions[0x0=>0x1]	955543	1			T24	9		T25	7244		T26	228
all_pins[17]	transitions[0x1=>0x0]	944831	1			T24	2		T25	7201		T26	242
all_pins[18]	values[0x0]	2601525	1			T23	31		T24	53		T25	20062
all_pins[18]	values[0x1]	1580833	1			T24	5		T25	12908		T26	498
all_pins[18]	transitions[0x0=>0x1]	946547	1			T24	2		T25	7463		T26	308
all_pins[18]	transitions[0x1=>0x0]	956739	1			T24	9		T25	6981		T26	205
all_pins[19]	values[0x0]	2597287	1			T23	31		T24	51		T25	21039
all_pins[19]	values[0x1]	1585071	1			T24	7		T25	11931		T26	465
all_pins[19]	transitions[0x0=>0x1]	947577	1			T24	7		T25	6924		T26	231
all_pins[19]	transitions[0x1=>0x0]	943339	1			T24	5		T25	7901		T26	264
all_pins[20]	values[0x0]	2600655	1			T23	31		T24	48		T25	20783
all_pins[20]	values[0x1]	1581703	1			T24	10		T25	12187		T26	481
all_pins[20]	transitions[0x0=>0x1]	944661	1			T24	10		T25	7560		T26	286
all_pins[20]	transitions[0x1=>0x0]	948029	1			T24	7		T25	7304		T26	270
all_pins[21]	values[0x0]	2597561	1			T23	31		T24	54		T25	20416
all_pins[21]	values[0x1]	1584797	1			T24	4		T25	12554		T26	425
all_pins[21]	transitions[0x0=>0x1]	947858	1			T24	4		T25	7668		T26	288
all_pins[21]	transitions[0x1=>0x0]	944764	1			T24	10		T25	7301		T26	344
all_pins[22]	values[0x0]	2599379	1			T23	31		T24	58		T25	20304
all_pins[22]	values[0x1]	1582979	1			T25	12666		T26	403		T29	32595
all_pins[22]	transitions[0x0=>0x1]	947679	1			T25	7546		T26	240		T29	19592
all_pins[22]	transitions[0x1=>0x0]	949497	1			T24	4		T25	7434		T26	262
all_pins[23]	values[0x0]	2597512	1			T23	31		T24	54		T25	20370
all_pins[23]	values[0x1]	1584846	1			T24	4		T25	12600		T26	366
all_pins[23]	transitions[0x0=>0x1]	949811	1			T24	4		T25	7234		T26	245
all_pins[23]	transitions[0x1=>0x0]	947944	1			T25	7300		T26	282		T29	20215
all_pins[24]	values[0x0]	2599084	1			T23	31		T24	50		T25	20358
all_pins[24]	values[0x1]	1583274	1			T24	8		T25	12612		T26	388
all_pins[24]	transitions[0x0=>0x1]	946438	1			T24	4		T25	7417		T26	265
all_pins[24]	transitions[0x1=>0x0]	948010	1			T25	7405		T26	243		T29	19771
all_pins[25]	values[0x0]	2599762	1			T23	31		T24	47		T25	20824
all_pins[25]	values[0x1]	1582596	1			T24	11		T25	12146		T26	385
all_pins[25]	transitions[0x0=>0x1]	951074	1			T24	7		T25	7117		T26	234
all_pins[25]	transitions[0x1=>0x0]	951752	1			T24	4		T25	7583		T26	237
all_pins[26]	values[0x0]	2601488	1			T23	31		T24	53		T25	20649
all_pins[26]	values[0x1]	1580870	1			T24	5		T25	12321		T26	378
all_pins[26]	transitions[0x0=>0x1]	945693	1			T24	1		T25	7658		T26	248
all_pins[26]	transitions[0x1=>0x0]	947419	1			T24	7		T25	7483		T26	255
all_pins[27]	values[0x0]	2599391	1			T23	31		T24	49		T25	20580
all_pins[27]	values[0x1]	1582967	1			T24	9		T25	12390		T26	323
all_pins[27]	transitions[0x0=>0x1]	951167	1			T24	5		T25	7279		T26	255
all_pins[27]	transitions[0x1=>0x0]	949070	1			T24	1		T25	7210		T26	310
all_pins[28]	values[0x0]	2599603	1			T23	31		T24	57		T25	20610
all_pins[28]	values[0x1]	1582755	1			T24	1		T25	12360		T26	465
all_pins[28]	transitions[0x0=>0x1]	946160	1			T25	7649		T26	342		T29	19837
all_pins[28]	transitions[0x1=>0x0]	946372	1			T24	8		T25	7679		T26	200
all_pins[29]	values[0x0]	2600018	1			T23	31		T24	45		T25	20327
all_pins[29]	values[0x1]	1582340	1			T24	13		T25	12643		T26	525
all_pins[29]	transitions[0x0=>0x1]	948180	1			T24	13		T25	7506		T26	280
all_pins[29]	transitions[0x1=>0x0]	948595	1			T24	1		T25	7223		T26	220
all_pins[30]	values[0x0]	2599959	1			T23	31		T24	52		T25	20541
all_pins[30]	values[0x1]	1582399	1			T24	6		T25	12429		T26	558
all_pins[30]	transitions[0x0=>0x1]	949115	1			T25	7421		T26	324		T29	20422
all_pins[30]	transitions[0x1=>0x0]	949056	1			T24	7		T25	7635		T26	291
all_pins[31]	values[0x0]	2596697	1			T23	31		T24	47		T25	20931
all_pins[31]	values[0x1]	1585661	1			T24	11		T25	12039		T26	417
all_pins[31]	transitions[0x0=>0x1]	948419	1			T24	5		T25	7366		T26	212
all_pins[31]	transitions[0x1=>0x0]	945157	1			T25	7756		T26	353		T29	19751