Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13646563	1			T23	1		T24	121		T25	104162
all_values[1]	13646563	1			T23	1		T24	121		T25	104162
all_values[2]	13646563	1			T23	1		T24	121		T25	104162
all_values[3]	13646563	1			T23	1		T24	121		T25	104162
all_values[4]	13646563	1			T23	1		T24	121		T25	104162
all_values[5]	13646563	1			T23	1		T24	121		T25	104162
all_values[6]	13646563	1			T23	1		T24	121		T25	104162
all_values[7]	13646563	1			T23	1		T24	121		T25	104162
all_values[8]	13646563	1			T23	1		T24	121		T25	104162
all_values[9]	13646563	1			T23	1		T24	121		T25	104162
all_values[10]	13646563	1			T23	1		T24	121		T25	104162
all_values[11]	13646563	1			T23	1		T24	121		T25	104162
all_values[12]	13646563	1			T23	1		T24	121		T25	104162
all_values[13]	13646563	1			T23	1		T24	121		T25	104162
all_values[14]	13646563	1			T23	1		T24	121		T25	104162
all_values[15]	13646563	1			T23	1		T24	121		T25	104162
all_values[16]	13646563	1			T23	1		T24	121		T25	104162
all_values[17]	13646563	1			T23	1		T24	121		T25	104162
all_values[18]	13646563	1			T23	1		T24	121		T25	104162
all_values[19]	13646563	1			T23	1		T24	121		T25	104162
all_values[20]	13646563	1			T23	1		T24	121		T25	104162
all_values[21]	13646563	1			T23	1		T24	121		T25	104162
all_values[22]	13646563	1			T23	1		T24	121		T25	104162
all_values[23]	13646563	1			T23	1		T24	121		T25	104162
all_values[24]	13646563	1			T23	1		T24	121		T25	104162
all_values[25]	13646563	1			T23	1		T24	121		T25	104162
all_values[26]	13646563	1			T23	1		T24	121		T25	104162
all_values[27]	13646563	1			T23	1		T24	121		T25	104162
all_values[28]	13646563	1			T23	1		T24	121		T25	104162
all_values[29]	13646563	1			T23	1		T24	121		T25	104162
all_values[30]	13646563	1			T23	1		T24	121		T25	104162
all_values[31]	13646563	1			T23	1		T24	121		T25	104162

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249846660

1

T23

32

T24

3288

T25

184353

auto[1]

186843356

1

T24

584

T25

148965

T26

52232

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98781133

1

T23

32

T24

2602

T25

624154

auto[1]

337908883

1

T24

1270

T25

270903

T26

93074

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

431876733

1

T23

32

T24

3662

T25

328785

auto[1]

4813283

1

T24

210

T25

45325

T29

95047

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2528077	1			T23	1		T24	92		T25	14954
all_values[0]	auto[0]	auto[0]	auto[1]	5235111	1			T24	17		T25	42218		T26	1399
all_values[0]	auto[0]	auto[1]	auto[0]	554751	1			T24	7		T25	4596		T26	85
all_values[0]	auto[0]	auto[1]	auto[1]	5178038	1			T24	1		T25	40999		T26	1486
all_values[0]	auto[1]	auto[0]	auto[1]	75792	1			T24	4		T25	700		T29	1503
all_values[0]	auto[1]	auto[1]	auto[1]	74794	1			T25	695		T29	1467		T1	9
all_values[1]	auto[0]	auto[0]	auto[0]	2518999	1			T23	1		T24	73		T25	14768
all_values[1]	auto[0]	auto[0]	auto[1]	5203530	1			T24	15		T25	42300		T26	1625
all_values[1]	auto[0]	auto[1]	auto[0]	578053	1			T24	9		T25	4942		T26	63
all_values[1]	auto[0]	auto[1]	auto[1]	5195618	1			T24	17		T25	40743		T26	1328
all_values[1]	auto[1]	auto[0]	auto[1]	75820	1			T24	5		T25	691		T29	1514
all_values[1]	auto[1]	auto[1]	auto[1]	74543	1			T24	2		T25	718		T29	1417
all_values[2]	auto[0]	auto[0]	auto[0]	2515190	1			T23	1		T24	70		T25	14888
all_values[2]	auto[0]	auto[0]	auto[1]	5225024	1			T24	34		T25	41010		T26	1759
all_values[2]	auto[0]	auto[1]	auto[0]	575823	1			T24	6		T25	4908		T26	82
all_values[2]	auto[0]	auto[1]	auto[1]	5179958	1			T24	6		T25	41956		T26	1198
all_values[2]	auto[1]	auto[0]	auto[1]	75673	1			T24	5		T25	750		T29	1490
all_values[2]	auto[1]	auto[1]	auto[1]	74895	1			T25	650		T29	1500		T1	10
all_values[3]	auto[0]	auto[0]	auto[0]	2518508	1			T23	1		T24	77		T25	15144
all_values[3]	auto[0]	auto[0]	auto[1]	5194214	1			T24	26		T25	43221		T26	1268
all_values[3]	auto[0]	auto[1]	auto[0]	563719	1			T24	4		T25	4673		T26	143
all_values[3]	auto[0]	auto[1]	auto[1]	5219728	1			T24	9		T25	39668		T26	1679
all_values[3]	auto[1]	auto[0]	auto[1]	75159	1			T24	2		T25	746		T29	1472
all_values[3]	auto[1]	auto[1]	auto[1]	75235	1			T24	3		T25	710		T29	1497
all_values[4]	auto[0]	auto[0]	auto[0]	2511040	1			T23	1		T24	76		T25	15036
all_values[4]	auto[0]	auto[0]	auto[1]	5219547	1			T24	18		T25	42065		T26	1542
all_values[4]	auto[0]	auto[1]	auto[0]	568215	1			T24	6		T25	4456		T26	157
all_values[4]	auto[0]	auto[1]	auto[1]	5196740	1			T24	16		T25	41177		T26	1362
all_values[4]	auto[1]	auto[0]	auto[1]	75473	1			T24	3		T25	690		T29	1544
all_values[4]	auto[1]	auto[1]	auto[1]	75548	1			T24	2		T25	738		T29	1492
all_values[5]	auto[0]	auto[0]	auto[0]	2516753	1			T23	1		T24	78		T25	14716
all_values[5]	auto[0]	auto[0]	auto[1]	5186513	1			T24	27		T25	41271		T26	1615
all_values[5]	auto[0]	auto[1]	auto[0]	565334	1			T24	1		T25	4717		T26	87
all_values[5]	auto[0]	auto[1]	auto[1]	5227082	1			T24	10		T25	42102		T26	1342
all_values[5]	auto[1]	auto[0]	auto[1]	75547	1			T24	4		T25	681		T29	1560
all_values[5]	auto[1]	auto[1]	auto[1]	75334	1			T24	1		T25	675		T29	1484
all_values[6]	auto[0]	auto[0]	auto[0]	2511488	1			T23	1		T24	65		T25	14649
all_values[6]	auto[0]	auto[0]	auto[1]	5209266	1			T24	39		T25	44058		T26	1154
all_values[6]	auto[0]	auto[1]	auto[0]	585840	1			T24	1		T25	4542		T26	132
all_values[6]	auto[0]	auto[1]	auto[1]	5189744	1			T24	10		T25	39490		T26	1703
all_values[6]	auto[1]	auto[0]	auto[1]	75268	1			T24	5		T25	729		T29	1512
all_values[6]	auto[1]	auto[1]	auto[1]	74957	1			T24	1		T25	694		T29	1483
all_values[7]	auto[0]	auto[0]	auto[0]	2523519	1			T23	1		T24	70		T25	14999
all_values[7]	auto[0]	auto[0]	auto[1]	5229188	1			T24	34		T25	39724		T26	1261
all_values[7]	auto[0]	auto[1]	auto[0]	579333	1			T24	8		T25	4864		T26	116
all_values[7]	auto[0]	auto[1]	auto[1]	5164229	1			T24	4		T25	43144		T26	1717
all_values[7]	auto[1]	auto[0]	auto[1]	75368	1			T24	5		T25	657		T29	1447
all_values[7]	auto[1]	auto[1]	auto[1]	74926	1			T25	774		T29	1581		T1	14
all_values[8]	auto[0]	auto[0]	auto[0]	2526760	1			T23	1		T24	69		T25	15068
all_values[8]	auto[0]	auto[0]	auto[1]	5228975	1			T24	24		T25	45228		T26	1359
all_values[8]	auto[0]	auto[1]	auto[0]	571472	1			T24	15		T25	4432		T26	104
all_values[8]	auto[0]	auto[1]	auto[1]	5169046	1			T24	6		T25	38018		T26	1595
all_values[8]	auto[1]	auto[0]	auto[1]	75645	1			T24	4		T25	753		T29	1497
all_values[8]	auto[1]	auto[1]	auto[1]	74665	1			T24	3		T25	663		T29	1424
all_values[9]	auto[0]	auto[0]	auto[0]	2519809	1			T23	1		T24	71		T25	14311
all_values[9]	auto[0]	auto[0]	auto[1]	5206621	1			T24	25		T25	40399		T26	1425
all_values[9]	auto[0]	auto[1]	auto[0]	566861	1			T24	7		T25	4626		T26	115
all_values[9]	auto[0]	auto[1]	auto[1]	5203043	1			T24	11		T25	43429		T26	1470
all_values[9]	auto[1]	auto[0]	auto[1]	75110	1			T24	3		T25	732		T29	1468
all_values[9]	auto[1]	auto[1]	auto[1]	75119	1			T24	4		T25	665		T29	1486
all_values[10]	auto[0]	auto[0]	auto[0]	2519577	1			T23	1		T24	74		T25	14850
all_values[10]	auto[0]	auto[0]	auto[1]	5231616	1			T24	23		T25	39565		T26	1354
all_values[10]	auto[0]	auto[1]	auto[0]	574692	1			T24	13		T25	4577		T26	75
all_values[10]	auto[0]	auto[1]	auto[1]	5170621	1			T24	3		T25	43748		T26	1620
all_values[10]	auto[1]	auto[0]	auto[1]	75140	1			T24	6		T25	746		T29	1473
all_values[10]	auto[1]	auto[1]	auto[1]	74917	1			T24	2		T25	676		T29	1494
all_values[11]	auto[0]	auto[0]	auto[0]	2514405	1			T23	1		T24	71		T25	14567
all_values[11]	auto[0]	auto[0]	auto[1]	5204428	1			T24	22		T25	41960		T26	1358
all_values[11]	auto[0]	auto[1]	auto[0]	569136	1			T24	20		T25	4449		T26	155
all_values[11]	auto[0]	auto[1]	auto[1]	5208365	1			T24	2		T25	41763		T26	1534
all_values[11]	auto[1]	auto[0]	auto[1]	75281	1			T24	4		T25	745		T29	1530
all_values[11]	auto[1]	auto[1]	auto[1]	74948	1			T24	2		T25	678		T29	1384
all_values[12]	auto[0]	auto[0]	auto[0]	2510696	1			T23	1		T24	78		T25	14914
all_values[12]	auto[0]	auto[0]	auto[1]	5184315	1			T24	16		T25	41293		T26	1186
all_values[12]	auto[0]	auto[1]	auto[0]	566233	1			T24	6		T25	4715		T26	101
all_values[12]	auto[0]	auto[1]	auto[1]	5234756	1			T24	15		T25	41822		T26	1761
all_values[12]	auto[1]	auto[0]	auto[1]	75188	1			T24	5		T25	712		T29	1443
all_values[12]	auto[1]	auto[1]	auto[1]	75375	1			T24	1		T25	706		T29	1479
all_values[13]	auto[0]	auto[0]	auto[0]	2510498	1			T23	1		T24	69		T25	14566
all_values[13]	auto[0]	auto[0]	auto[1]	5213585	1			T24	27		T25	41415		T26	1322
all_values[13]	auto[0]	auto[1]	auto[0]	571479	1			T24	6		T25	4700		T26	141
all_values[13]	auto[0]	auto[1]	auto[1]	5200955	1			T24	9		T25	42152		T26	1624
all_values[13]	auto[1]	auto[0]	auto[1]	74833	1			T24	7		T25	674		T29	1456
all_values[13]	auto[1]	auto[1]	auto[1]	75213	1			T24	3		T25	655		T29	1507
all_values[14]	auto[0]	auto[0]	auto[0]	2514026	1			T23	1		T24	80		T25	14845
all_values[14]	auto[0]	auto[0]	auto[1]	5222387	1			T24	19		T25	42275		T26	1416
all_values[14]	auto[0]	auto[1]	auto[0]	569372	1			T24	7		T25	4465		T26	272
all_values[14]	auto[0]	auto[1]	auto[1]	5190541	1			T24	9		T25	41152		T26	1353
all_values[14]	auto[1]	auto[0]	auto[1]	75443	1			T24	4		T25	704		T29	1463
all_values[14]	auto[1]	auto[1]	auto[1]	74794	1			T24	2		T25	721		T29	1513
all_values[15]	auto[0]	auto[0]	auto[0]	2507528	1			T23	1		T24	65		T25	14835
all_values[15]	auto[0]	auto[0]	auto[1]	5228472	1			T24	22		T25	42299		T26	1272
all_values[15]	auto[0]	auto[1]	auto[0]	570818	1			T24	12		T25	4325		T26	118
all_values[15]	auto[0]	auto[1]	auto[1]	5189281	1			T24	16		T25	41270		T26	1664
all_values[15]	auto[1]	auto[0]	auto[1]	75430	1			T24	4		T25	658		T29	1496
all_values[15]	auto[1]	auto[1]	auto[1]	75034	1			T24	2		T25	775		T29	1478
all_values[16]	auto[0]	auto[0]	auto[0]	2517263	1			T23	1		T24	79		T25	15322
all_values[16]	auto[0]	auto[0]	auto[1]	5223915	1			T24	29		T25	41893		T26	1609
all_values[16]	auto[0]	auto[1]	auto[0]	573467	1			T25	4569		T26	48		T29	14419
all_values[16]	auto[0]	auto[1]	auto[1]	5181572	1			T24	6		T25	40974		T26	1379
all_values[16]	auto[1]	auto[0]	auto[1]	74993	1			T24	7		T25	690		T29	1499
all_values[16]	auto[1]	auto[1]	auto[1]	75353	1			T25	714		T29	1481		T1	12
all_values[17]	auto[0]	auto[0]	auto[0]	2510326	1			T23	1		T24	76		T25	14775
all_values[17]	auto[0]	auto[0]	auto[1]	5205276	1			T24	11		T25	43310		T26	1485
all_values[17]	auto[0]	auto[1]	auto[0]	577693	1			T24	17		T25	4262		T26	149
all_values[17]	auto[0]	auto[1]	auto[1]	5203055	1			T24	12		T25	40352		T26	1330
all_values[17]	auto[1]	auto[0]	auto[1]	75322	1			T24	2		T25	780		T29	1473
all_values[17]	auto[1]	auto[1]	auto[1]	74891	1			T24	3		T25	683		T29	1458
all_values[18]	auto[0]	auto[0]	auto[0]	2514491	1			T23	1		T24	78		T25	14487
all_values[18]	auto[0]	auto[0]	auto[1]	5197333	1			T24	21		T25	40974		T26	1107
all_values[18]	auto[0]	auto[1]	auto[0]	575568	1			T24	8		T25	4320		T26	189
all_values[18]	auto[0]	auto[1]	auto[1]	5208559	1			T24	6		T25	42946		T26	1770
all_values[18]	auto[1]	auto[0]	auto[1]	75306	1			T24	8		T25	719		T29	1515
all_values[18]	auto[1]	auto[1]	auto[1]	75306	1			T25	716		T29	1424		T1	14
all_values[19]	auto[0]	auto[0]	auto[0]	2514525	1			T23	1		T24	75		T25	15039
all_values[19]	auto[0]	auto[0]	auto[1]	5200547	1			T24	25		T25	44035		T26	1177
all_values[19]	auto[0]	auto[1]	auto[0]	565419	1			T24	2		T25	4924		T26	127
all_values[19]	auto[0]	auto[1]	auto[1]	5215773	1			T24	8		T25	38726		T26	1702
all_values[19]	auto[1]	auto[0]	auto[1]	75176	1			T24	9		T25	753		T29	1484
all_values[19]	auto[1]	auto[1]	auto[1]	75123	1			T24	2		T25	685		T29	1495
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all_values[20]	auto[0]	auto[1]	auto[1]	5174668	1			T24	10		T25	39255		T26	1691
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all_values[21]	auto[1]	auto[1]	auto[1]	74654	1			T24	2		T25	695		T29	1448
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all_values[27]	auto[0]	auto[1]	auto[1]	5184539	1			T24	9		T25	43158		T26	1183
all_values[27]	auto[1]	auto[0]	auto[1]	75702	1			T24	5		T25	755		T29	1506
all_values[27]	auto[1]	auto[1]	auto[1]	74785	1			T24	3		T25	707		T29	1529
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all_values[28]	auto[0]	auto[0]	auto[1]	5207728	1			T24	34		T25	43545		T26	1163
all_values[28]	auto[0]	auto[1]	auto[0]	570240	1			T24	17		T25	4511		T26	210
all_values[28]	auto[0]	auto[1]	auto[1]	5204077	1			T25	39233		T26	1667		T29	113487
all_values[28]	auto[1]	auto[0]	auto[1]	75759	1			T24	4		T25	710		T29	1498
all_values[28]	auto[1]	auto[1]	auto[1]	74738	1			T24	1		T25	678		T29	1453
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all_values[29]	auto[0]	auto[1]	auto[0]	573324	1			T24	22		T25	4467		T26	50
all_values[29]	auto[0]	auto[1]	auto[1]	5199746	1			T24	12		T25	40697		T26	1634
all_values[29]	auto[1]	auto[0]	auto[1]	75181	1			T24	6		T25	714		T29	1461
all_values[29]	auto[1]	auto[1]	auto[1]	74860	1			T24	2		T25	666		T29	1454
all_values[30]	auto[0]	auto[0]	auto[0]	2516004	1			T23	1		T24	70		T25	15692
all_values[30]	auto[0]	auto[0]	auto[1]	5179061	1			T24	31		T25	41345		T26	1086
all_values[30]	auto[0]	auto[1]	auto[0]	572538	1			T24	4		T25	4501		T26	92
all_values[30]	auto[0]	auto[1]	auto[1]	5228536	1			T24	8		T25	41193		T26	1941
all_values[30]	auto[1]	auto[0]	auto[1]	75428	1			T24	8		T25	734		T29	1526
all_values[30]	auto[1]	auto[1]	auto[1]	74996	1			T25	697		T29	1476		T1	10
all_values[31]	auto[0]	auto[0]	auto[0]	2515701	1			T23	1		T24	71		T25	15430
all_values[31]	auto[0]	auto[0]	auto[1]	5243467	1			T24	29		T25	42896		T26	1663
all_values[31]	auto[0]	auto[1]	auto[0]	566661	1			T24	2		T25	4348		T26	95
all_values[31]	auto[0]	auto[1]	auto[1]	5170196	1			T24	13		T25	40097		T26	1309
all_values[31]	auto[1]	auto[0]	auto[1]	75406	1			T24	3		T25	745		T29	1471
all_values[31]	auto[1]	auto[1]	auto[1]	75132	1			T24	3		T25	646		T29	1507

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal