Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[1]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[2]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[3]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[4]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[5]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[6]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[7]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[8]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[9]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[10]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[11]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[12]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[13]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[14]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[15]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[16]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[17]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[18]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[19]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[20]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[21]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[22]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[23]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[24]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[25]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[26]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[27]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[28]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[29]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[30]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[31]	13387446	1			T23	31		T24	223		T25	101064

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254069735

1

T23

992

T24

3881

T25

110569

auto[1]

174328537

1

T24

3255

T25

212835

T26

39355

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

343032341

1

T23

992

T24

6623

T25

248572

auto[1]

85365931

1

T24

513

T25

748319

T27

281

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

318062581

1

T23

992

T24

5708

T25

228555

auto[1]

110335691

1

T24

1428

T25

948494

T27

1764

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4916770	1			T23	31		T24	73		T25	21743
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3682696	1			T24	67		T25	37721		T26	1259
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1344478	1			T24	4		T25	11906		T27	8
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1669336	1			T24	44		T25	1050		T27	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	444708	1			T24	11		T25	17109		T27	54
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1329458	1			T24	24		T25	11535		T27	6
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4933685	1			T23	31		T24	86		T25	21786
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3663380	1			T24	55		T25	38241		T26	1198
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1345453	1			T24	7		T25	11623		T27	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1666851	1			T24	54		T25	1084		T27	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	446733	1			T24	16		T25	16715		T27	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1331344	1			T24	5		T25	11615		T28	9
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4925394	1			T23	31		T24	133		T25	21606
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3670544	1			T24	47		T25	37994		T26	1205
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1337229	1			T24	5		T25	11746		T27	2
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1673531	1			T24	21		T25	1104		T27	22
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	449912	1			T24	12		T25	17107		T27	63
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1330836	1			T24	5		T25	11507		T27	4
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4922552	1			T23	31		T24	94		T25	21812
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3674429	1			T24	81		T25	37626		T26	1244
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1339622	1			T25	12263		T27	6		T28	14
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1674979	1			T24	16		T25	993		T27	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	449513	1			T24	18		T25	16737		T27	66
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1326351	1			T24	14		T25	11633		T27	6
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4921506	1			T23	31		T24	80		T25	21745
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3668559	1			T24	72		T25	37556		T26	1231
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1340078	1			T24	5		T25	12190		T27	4
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1671642	1			T24	16		T25	1044		T27	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	448775	1			T24	14		T25	16684		T27	32
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1336886	1			T24	36		T25	11845		T29	27240
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4921227	1			T23	31		T24	92		T25	21821
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3672196	1			T24	70		T25	37882		T26	1274
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1344578	1			T24	7		T25	11999		T27	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1672519	1			T24	23		T25	1095		T27	24
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	447218	1			T24	17		T25	16504		T27	55
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1329708	1			T24	14		T25	11763		T27	6
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4931780	1			T23	31		T24	94		T25	21914
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3675663	1			T24	99		T25	37423		T26	1239
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1335633	1			T24	3		T25	11791		T27	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1672206	1			T24	15		T25	1152		T27	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	445642	1			T24	6		T25	17508		T27	61
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1326522	1			T24	6		T25	11276		T27	6
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4923173	1			T23	31		T24	71		T25	21843
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3670205	1			T24	89		T25	38249		T26	1245
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1341009	1			T24	2		T25	11288		T27	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1670256	1			T24	34		T25	969		T27	11
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	446782	1			T24	12		T25	17102		T27	22
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1336021	1			T24	15		T25	11613		T29	26870
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4929848	1			T23	31		T24	96		T25	21717
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3664741	1			T24	54		T25	38130		T26	1247
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1340513	1			T24	8		T25	11654		T28	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1676973	1			T24	37		T25	1053		T27	21
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	447291	1			T24	25		T25	16889		T27	77
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1328080	1			T24	3		T25	11621		T27	2
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4934065	1			T23	31		T24	89		T25	21346
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3667632	1			T24	93		T25	38127		T26	1236
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1341840	1			T24	2		T25	12114		T27	12
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1667085	1			T24	28		T25	1141		T27	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	445693	1			T24	8		T25	16963		T27	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1331131	1			T24	3		T25	11373		T28	12
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4920500	1			T23	31		T24	62		T25	21891
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3675994	1			T24	106		T25	37968		T26	1270
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1350220	1			T24	10		T25	11927		T27	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1664969	1			T24	27		T25	1038		T27	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	443767	1			T24	6		T25	16722		T27	33
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1331996	1			T24	12		T25	11518		T28	19
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4930150	1			T23	31		T24	108		T25	21618
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3679389	1			T24	81		T25	37512		T26	1235
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1339925	1			T24	17		T25	12349		T28	23
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1663381	1			T24	9		T25	1038		T27	30
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	445082	1			T24	2		T25	16802		T27	56
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1329519	1			T24	6		T25	11745		T27	4
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4927272	1			T23	31		T24	53		T25	21741
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3665167	1			T24	72		T25	37601		T26	1240
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1341503	1			T24	9		T25	12401		T27	12
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1673721	1			T24	44		T25	1046		T27	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	447240	1			T24	17		T25	16987		T27	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1332543	1			T24	28		T25	11288		T28	13
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4919400	1			T23	31		T24	62		T25	21775
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3676633	1			T24	115		T25	37766		T26	1266
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1341624	1			T24	3		T25	11639		T27	6
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1674674	1			T24	19		T25	1114		T27	20
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	448094	1			T24	10		T25	17075		T27	60
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1327021	1			T24	14		T25	11695		T27	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4927965	1			T23	31		T24	110		T25	21702
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3671953	1			T24	66		T25	38124		T26	1254
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1347865	1			T24	2		T25	12476		T27	2
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1662405	1			T24	27		T25	1066		T27	19
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	444851	1			T24	7		T25	16378		T27	58
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1332407	1			T24	11		T25	11318		T27	4
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4919846	1			T23	31		T24	88		T25	21670
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3672333	1			T24	92		T25	37159		T26	1238
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1339951	1			T24	3		T25	11719		T27	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1673549	1			T24	14		T25	1213		T27	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	446138	1			T24	18		T25	17356		T27	11
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1335629	1			T24	8		T25	11947		T28	10
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4924406	1			T23	31		T24	100		T25	21767
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3671226	1			T24	66		T25	37959		T26	1233
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1337626	1			T24	6		T25	11655		T27	8
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1675560	1			T24	24		T25	1033		T27	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	449685	1			T24	8		T25	17027		T27	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1328943	1			T24	19		T25	11623		T27	2
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4939392	1			T23	31		T24	117		T25	21634
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3662232	1			T24	65		T25	37689		T26	1227
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1337824	1			T24	2		T25	11400		T27	10
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1673922	1			T24	20		T25	1132		T27	3
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	447169	1			T24	11		T25	17242		T27	19
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1326907	1			T24	8		T25	11967		T27	8
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4926192	1			T23	31		T24	103		T25	21609
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3677815	1			T24	100		T25	37968		T26	1256
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1331177	1			T24	4		T25	11862		T27	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1678019	1			T24	8		T25	1075		T27	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	448969	1			T24	4		T25	16693		T27	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1325274	1			T24	4		T25	11857		T27	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4930304	1			T23	31		T24	99		T25	21684
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3670826	1			T24	84		T25	38409		T26	1224
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1339165	1			T24	10		T25	11110		T27	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1674256	1			T24	18		T25	1054		T27	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	447777	1			T24	4		T25	17549		T27	24
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1325118	1			T24	8		T25	11258		T28	6
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4943168	1			T23	31		T24	77		T25	21659
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3659457	1			T24	93		T25	37837		T26	1218
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1334800	1			T24	3		T25	11533		T27	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1676151	1			T24	25		T25	1069		T27	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	450523	1			T24	12		T25	17398		T27	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1323347	1			T24	13		T25	11568		T27	2
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4930384	1			T23	31		T24	95		T25	21673
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3672602	1			T24	83		T25	37852		T26	1208
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1337410	1			T24	8		T25	11685		T27	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1673471	1			T24	13		T25	1066		T27	27
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	446214	1			T24	9		T25	16852		T27	50
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1327365	1			T24	15		T25	11936		T27	2
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4938377	1			T23	31		T24	59		T25	21519
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3664047	1			T24	114		T25	38096		T26	1245
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1339431	1			T24	6		T25	11561		T27	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1669433	1			T24	23		T25	1118		T27	21
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	448808	1			T24	13		T25	16946		T27	83
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1327350	1			T24	8		T25	11824		T27	4
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4935541	1			T23	31		T24	117		T25	21645
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3674800	1			T24	66		T25	38382		T26	1170
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1336576	1			T24	11		T25	11699		T27	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1671327	1			T24	26		T25	1069		T27	31
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	448157	1			T24	3		T25	16728		T27	57
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1321045	1			T25	11541		T27	4		T28	18
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4922863	1			T23	31		T24	87		T25	21748
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3678813	1			T24	73		T25	37986		T26	1231
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1338486	1			T24	9		T25	11845		T27	11
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1675191	1			T24	25		T25	1040		T28	12
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	447248	1			T24	10		T25	16751		T27	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1324845	1			T24	19		T25	11694		T28	13
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4921563	1			T23	31		T24	106		T25	21794
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3675981	1			T24	60		T25	37953		T26	1217
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1339817	1			T24	7		T25	11808		T27	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1672787	1			T24	26		T25	1018		T27	20
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	447730	1			T24	17		T25	16481		T27	78
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1329568	1			T24	7		T25	12010		T27	10
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4929074	1			T23	31		T24	102		T25	21609
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3675618	1			T24	102		T25	38091		T26	1220
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1335918	1			T24	4		T25	12026		T27	11
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1674744	1			T24	7		T25	1025		T28	9
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	446687	1			T24	5		T25	16790		T27	4
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1325405	1			T24	3		T25	11523		T28	16
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4931838	1			T23	31		T24	90		T25	21542
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3674989	1			T24	94		T25	38663		T26	1218
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1339206	1			T24	5		T25	11132		T27	6
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1671231	1			T24	21		T25	1157		T27	19
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	448236	1			T24	10		T25	17328		T27	84
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1321946	1			T24	3		T25	11242		T27	6
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4927909	1			T23	31		T24	107		T25	21713
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3677494	1			T24	76		T25	37629		T26	1181
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1336640	1			T24	7		T25	11724		T27	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1672403	1			T24	20		T25	1094		T28	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	446570	1			T24	7		T25	17219		T28	69
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1326430	1			T24	6		T25	11685		T28	10
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4932071	1			T23	31		T24	73		T25	21841
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3667109	1			T24	113		T25	37728		T26	1205
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1335388	1			T25	11463		T27	6		T28	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1678084	1			T24	9		T25	1096		T27	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	449770	1			T24	20		T25	17396		T27	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1325024	1			T24	8		T25	11540		T28	27
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4928941	1			T23	31		T24	98		T25	21643
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3676266	1			T24	90		T25	38269		T26	1221
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1332538	1			T24	5		T25	11408		T27	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1672676	1			T24	19		T25	985		T27	23
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	448884	1			T24	10		T25	17385		T27	84
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1328141	1			T24	1		T25	11374		T27	8
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4932590	1			T23	31		T24	117		T25	21798
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3673615	1			T24	45		T25	38510		T26	1200
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1334908	1			T24	13		T25	11850		T27	8
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1674226	1			T24	44		T25	1013		T27	29
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	446767	1			T24	4		T25	16354		T27	63
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1325340	1			T25	11539		T27	8		T28	6

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal