Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[1]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[2]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[3]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[4]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[5]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[6]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[7]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[8]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[9]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[10]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[11]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[12]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[13]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[14]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[15]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[16]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[17]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[18]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[19]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[20]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[21]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[22]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[23]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[24]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[25]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[26]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[27]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[28]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[29]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[30]	13387446	1			T23	31		T24	223		T25	101064
bins_for_gpio_bits[31]	13387446	1			T23	31		T24	223		T25	101064

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254069735

1

T23

992

T24

3881

T25

110569

auto[1]

174328537

1

T24

3255

T25

212835

T26

39355

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254062040

1

T23

992

T24

3876

T25

110595

auto[1]

174336232

1

T24

3260

T25

212809

T26

39355

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7692780	1			T23	31		T24	120		T25	32633
bins_for_gpio_bits[0]	auto[0]	auto[1]	237554	1			T25	2071		T27	1		T28	3
bins_for_gpio_bits[0]	auto[1]	auto[0]	237804	1			T24	1		T25	2066		T27	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	5219308	1			T24	102		T25	64294		T26	1259
bins_for_gpio_bits[1]	auto[0]	auto[0]	7707302	1			T23	31		T24	147		T25	32490
bins_for_gpio_bits[1]	auto[0]	auto[1]	238440	1			T25	2010		T27	3		T28	3
bins_for_gpio_bits[1]	auto[1]	auto[0]	238687	1			T25	2003		T27	3		T28	3
bins_for_gpio_bits[1]	auto[1]	auto[1]	5203017	1			T24	76		T25	64561		T26	1198
bins_for_gpio_bits[2]	auto[0]	auto[0]	7698170	1			T23	31		T24	159		T25	32419
bins_for_gpio_bits[2]	auto[0]	auto[1]	237775	1			T25	2046		T27	1		T28	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	237984	1			T25	2037		T27	1		T28	3
bins_for_gpio_bits[2]	auto[1]	auto[1]	5213517	1			T24	64		T25	64562		T26	1205
bins_for_gpio_bits[3]	auto[0]	auto[0]	7699433	1			T23	31		T24	109		T25	33034
bins_for_gpio_bits[3]	auto[0]	auto[1]	237473	1			T25	2047		T27	1		T28	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	237720	1			T24	1		T25	2034		T27	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	5212820	1			T24	113		T25	63949		T26	1244
bins_for_gpio_bits[4]	auto[0]	auto[0]	7694656	1			T23	31		T24	99		T25	32925
bins_for_gpio_bits[4]	auto[0]	auto[1]	238315	1			T25	2062		T27	2		T28	1
bins_for_gpio_bits[4]	auto[1]	auto[0]	238570	1			T24	2		T25	2054		T27	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	5215905	1			T24	122		T25	64023		T26	1231
bins_for_gpio_bits[5]	auto[0]	auto[0]	7699917	1			T23	31		T24	121		T25	32876
bins_for_gpio_bits[5]	auto[0]	auto[1]	238142	1			T24	1		T25	2043		T27	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	238407	1			T24	1		T25	2039		T27	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	5210980	1			T24	100		T25	64106		T26	1274
bins_for_gpio_bits[6]	auto[0]	auto[0]	7701290	1			T23	31		T24	112		T25	32816
bins_for_gpio_bits[6]	auto[0]	auto[1]	238098	1			T25	2049		T27	1		T28	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	238329	1			T25	2041		T27	1		T28	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	5209729	1			T24	111		T25	64158		T26	1239
bins_for_gpio_bits[7]	auto[0]	auto[0]	7694930	1			T23	31		T24	105		T25	32066
bins_for_gpio_bits[7]	auto[0]	auto[1]	239290	1			T24	1		T25	2041		T27	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	239508	1			T24	2		T25	2034		T27	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	5213718	1			T24	115		T25	64923		T26	1245
bins_for_gpio_bits[8]	auto[0]	auto[0]	7709589	1			T23	31		T24	141		T25	32370
bins_for_gpio_bits[8]	auto[0]	auto[1]	237503	1			T25	2064		T28	1		T29	4729
bins_for_gpio_bits[8]	auto[1]	auto[0]	237745	1			T25	2054		T28	1		T29	4730
bins_for_gpio_bits[8]	auto[1]	auto[1]	5202609	1			T24	82		T25	64576		T26	1247
bins_for_gpio_bits[9]	auto[0]	auto[0]	7704835	1			T23	31		T24	119		T25	32534
bins_for_gpio_bits[9]	auto[0]	auto[1]	237914	1			T25	2072		T27	4		T28	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	238155	1			T25	2067		T27	4		T28	2
bins_for_gpio_bits[9]	auto[1]	auto[1]	5206542	1			T24	104		T25	64391		T26	1236
bins_for_gpio_bits[10]	auto[0]	auto[0]	7697074	1			T23	31		T24	98		T25	32812
bins_for_gpio_bits[10]	auto[0]	auto[1]	238373	1			T24	1		T25	2052		T27	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	238615	1			T24	1		T25	2044		T27	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	5213384	1			T24	123		T25	64156		T26	1270
bins_for_gpio_bits[11]	auto[0]	auto[0]	7695150	1			T23	31		T24	134		T25	32916
bins_for_gpio_bits[11]	auto[0]	auto[1]	238098	1			T25	2099		T28	3		T29	4792
bins_for_gpio_bits[11]	auto[1]	auto[0]	238306	1			T25	2089		T28	3		T29	4792
bins_for_gpio_bits[11]	auto[1]	auto[1]	5215892	1			T24	89		T25	63960		T26	1235
bins_for_gpio_bits[12]	auto[0]	auto[0]	7704066	1			T23	31		T24	104		T25	33115
bins_for_gpio_bits[12]	auto[0]	auto[1]	238220	1			T24	2		T25	2084		T27	4
bins_for_gpio_bits[12]	auto[1]	auto[0]	238430	1			T24	2		T25	2073		T27	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	5206730	1			T24	115		T25	63792		T26	1240
bins_for_gpio_bits[13]	auto[0]	auto[0]	7697707	1			T23	31		T24	83		T25	32519
bins_for_gpio_bits[13]	auto[0]	auto[1]	237775	1			T24	1		T25	2015		T27	1
bins_for_gpio_bits[13]	auto[1]	auto[0]	237991	1			T24	1		T25	2009		T27	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	5213973	1			T24	138		T25	64521		T26	1266
bins_for_gpio_bits[14]	auto[0]	auto[0]	7699642	1			T23	31		T24	138		T25	33126
bins_for_gpio_bits[14]	auto[0]	auto[1]	238361	1			T24	1		T25	2126		T27	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	238593	1			T24	1		T25	2118		T27	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5210850	1			T24	83		T25	63694		T26	1254
bins_for_gpio_bits[15]	auto[0]	auto[0]	7694314	1			T23	31		T24	105		T25	32594
bins_for_gpio_bits[15]	auto[0]	auto[1]	238789	1			T25	2016		T27	1		T28	1
bins_for_gpio_bits[15]	auto[1]	auto[0]	239032	1			T25	2008		T27	1		T28	1
bins_for_gpio_bits[15]	auto[1]	auto[1]	5215311	1			T24	118		T25	64446		T26	1238
bins_for_gpio_bits[16]	auto[0]	auto[0]	7699157	1			T23	31		T24	129		T25	32406
bins_for_gpio_bits[16]	auto[0]	auto[1]	238211	1			T24	1		T25	2054		T27	4
bins_for_gpio_bits[16]	auto[1]	auto[0]	238435	1			T24	1		T25	2049		T27	4
bins_for_gpio_bits[16]	auto[1]	auto[1]	5211643	1			T24	92		T25	64555		T26	1233
bins_for_gpio_bits[17]	auto[0]	auto[0]	7712799	1			T23	31		T24	138		T25	32193
bins_for_gpio_bits[17]	auto[0]	auto[1]	238113	1			T24	1		T25	1978		T27	4
bins_for_gpio_bits[17]	auto[1]	auto[0]	238339	1			T24	1		T25	1973		T27	4
bins_for_gpio_bits[17]	auto[1]	auto[1]	5198195	1			T24	83		T25	64920		T26	1227
bins_for_gpio_bits[18]	auto[0]	auto[0]	7697499	1			T23	31		T24	115		T25	32542
bins_for_gpio_bits[18]	auto[0]	auto[1]	237641	1			T25	2007		T27	2		T29	4906
bins_for_gpio_bits[18]	auto[1]	auto[0]	237889	1			T25	2004		T27	2		T29	4906
bins_for_gpio_bits[18]	auto[1]	auto[1]	5214417	1			T24	108		T25	64511		T26	1256
bins_for_gpio_bits[19]	auto[0]	auto[0]	7705431	1			T23	31		T24	126		T25	31850
bins_for_gpio_bits[19]	auto[0]	auto[1]	238097	1			T24	1		T25	2009		T27	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	238294	1			T24	1		T25	1998		T27	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	5205624	1			T24	95		T25	65207		T26	1224
bins_for_gpio_bits[20]	auto[0]	auto[0]	7716228	1			T23	31		T24	104		T25	32256
bins_for_gpio_bits[20]	auto[0]	auto[1]	237640	1			T24	1		T25	2018		T27	3
bins_for_gpio_bits[20]	auto[1]	auto[0]	237891	1			T24	1		T25	2005		T27	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	5195687	1			T24	117		T25	64785		T26	1218
bins_for_gpio_bits[21]	auto[0]	auto[0]	7703213	1			T23	31		T24	115		T25	32379
bins_for_gpio_bits[21]	auto[0]	auto[1]	237777	1			T24	1		T25	2051		T27	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	238052	1			T24	1		T25	2045		T27	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5208404	1			T24	106		T25	64589		T26	1208
bins_for_gpio_bits[22]	auto[0]	auto[0]	7708259	1			T23	31		T24	87		T25	32122
bins_for_gpio_bits[22]	auto[0]	auto[1]	238731	1			T24	1		T25	2088		T27	1
bins_for_gpio_bits[22]	auto[1]	auto[0]	238982	1			T24	1		T25	2076		T27	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	5201474	1			T24	134		T25	64778		T26	1245
bins_for_gpio_bits[23]	auto[0]	auto[0]	7705318	1			T23	31		T24	154		T25	32358
bins_for_gpio_bits[23]	auto[0]	auto[1]	237834	1			T25	2064		T27	1		T28	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	238126	1			T25	2055		T27	1		T28	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5206168	1			T24	69		T25	64587		T26	1170
bins_for_gpio_bits[24]	auto[0]	auto[0]	7698345	1			T23	31		T24	120		T25	32563
bins_for_gpio_bits[24]	auto[0]	auto[1]	237971	1			T24	1		T25	2078		T27	4
bins_for_gpio_bits[24]	auto[1]	auto[0]	238195	1			T24	1		T25	2070		T27	4
bins_for_gpio_bits[24]	auto[1]	auto[1]	5212935	1			T24	101		T25	64353		T26	1231
bins_for_gpio_bits[25]	auto[0]	auto[0]	7695573	1			T23	31		T24	138		T25	32551
bins_for_gpio_bits[25]	auto[0]	auto[1]	238353	1			T24	1		T25	2072		T27	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	238594	1			T24	1		T25	2069		T27	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	5214926	1			T24	83		T25	64372		T26	1217
bins_for_gpio_bits[26]	auto[0]	auto[0]	7700912	1			T23	31		T24	113		T25	32599
bins_for_gpio_bits[26]	auto[0]	auto[1]	238563	1			T25	2068		T27	4		T28	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	238824	1			T25	2061		T27	4		T28	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	5209147	1			T24	110		T25	64336		T26	1220
bins_for_gpio_bits[27]	auto[0]	auto[0]	7704317	1			T23	31		T24	115		T25	31858
bins_for_gpio_bits[27]	auto[0]	auto[1]	237707	1			T24	1		T25	1979		T27	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	237958	1			T24	1		T25	1973		T27	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	5207464	1			T24	106		T25	65254		T26	1218
bins_for_gpio_bits[28]	auto[0]	auto[0]	7698724	1			T23	31		T24	134		T25	32537
bins_for_gpio_bits[28]	auto[0]	auto[1]	238005	1			T25	2004		T27	3		T28	2
bins_for_gpio_bits[28]	auto[1]	auto[0]	238228	1			T25	1994		T27	3		T28	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	5212489	1			T24	89		T25	64529		T26	1181
bins_for_gpio_bits[29]	auto[0]	auto[0]	7707559	1			T23	31		T24	82		T25	32373
bins_for_gpio_bits[29]	auto[0]	auto[1]	237729	1			T25	2036		T27	1		T28	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	237984	1			T25	2027		T27	1		T28	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	5204174	1			T24	141		T25	64628		T26	1205
bins_for_gpio_bits[30]	auto[0]	auto[0]	7695080	1			T23	31		T24	122		T25	32028
bins_for_gpio_bits[30]	auto[0]	auto[1]	238794	1			T25	2014		T27	1		T29	4817
bins_for_gpio_bits[30]	auto[1]	auto[0]	239075	1			T25	2008		T27	1		T29	4817
bins_for_gpio_bits[30]	auto[1]	auto[1]	5214497	1			T24	101		T25	65014		T26	1221
bins_for_gpio_bits[31]	auto[0]	auto[0]	7703222	1			T23	31		T24	174		T25	32602
bins_for_gpio_bits[31]	auto[0]	auto[1]	238263	1			T25	2071		T27	3		T28	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	238502	1			T25	2059		T27	3		T28	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	5207459	1			T24	49		T25	64332		T26	1200