Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7838980 |
1 |
|
|
T23 |
1 |
|
T24 |
113 |
|
T25 |
57872 |
| auto[1] |
5807583 |
1 |
|
|
T24 |
8 |
|
T25 |
46290 |
|
T26 |
1571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898026 |
1 |
|
|
T23 |
1 |
|
T24 |
121 |
|
T25 |
98072 |
| auto[1] |
748537 |
1 |
|
|
T25 |
6090 |
|
T26 |
319 |
|
T29 |
15453 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7806218 |
1 |
|
|
T23 |
1 |
|
T24 |
108 |
|
T25 |
55956 |
| auto[1] |
5840345 |
1 |
|
|
T24 |
13 |
|
T25 |
48206 |
|
T26 |
1597 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2563667 |
1 |
|
|
T24 |
13 |
|
T25 |
20446 |
|
T26 |
554 |
| auto[1] |
auto[0] |
auto[1] |
377815 |
1 |
|
|
T25 |
2979 |
|
T26 |
136 |
|
T29 |
7006 |
| auto[1] |
auto[1] |
auto[0] |
2528141 |
1 |
|
|
T25 |
21670 |
|
T26 |
724 |
|
T29 |
56991 |
| auto[1] |
auto[1] |
auto[1] |
370722 |
1 |
|
|
T25 |
3111 |
|
T26 |
183 |
|
T29 |
8447 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7798349 |
1 |
|
|
T23 |
1 |
|
T24 |
93 |
|
T25 |
57759 |
| auto[1] |
5848214 |
1 |
|
|
T24 |
28 |
|
T25 |
46403 |
|
T26 |
1391 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12894567 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98576 |
| auto[1] |
751996 |
1 |
|
|
T24 |
2 |
|
T25 |
5586 |
|
T26 |
256 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7779295 |
1 |
|
|
T23 |
1 |
|
T24 |
90 |
|
T25 |
58176 |
| auto[1] |
5867268 |
1 |
|
|
T24 |
31 |
|
T25 |
45986 |
|
T26 |
1369 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2565658 |
1 |
|
|
T24 |
20 |
|
T25 |
21243 |
|
T26 |
544 |
| auto[1] |
auto[0] |
auto[1] |
377483 |
1 |
|
|
T24 |
2 |
|
T25 |
3059 |
|
T26 |
126 |
| auto[1] |
auto[1] |
auto[0] |
2549614 |
1 |
|
|
T24 |
9 |
|
T25 |
19157 |
|
T26 |
569 |
| auto[1] |
auto[1] |
auto[1] |
374513 |
1 |
|
|
T25 |
2527 |
|
T26 |
130 |
|
T29 |
7768 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7826333 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
55161 |
| auto[1] |
5820230 |
1 |
|
|
T24 |
18 |
|
T25 |
49001 |
|
T26 |
1695 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897999 |
1 |
|
|
T23 |
1 |
|
T24 |
121 |
|
T25 |
98662 |
| auto[1] |
748564 |
1 |
|
|
T25 |
5500 |
|
T26 |
354 |
|
T29 |
16209 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7810039 |
1 |
|
|
T23 |
1 |
|
T24 |
97 |
|
T25 |
57880 |
| auto[1] |
5836524 |
1 |
|
|
T24 |
24 |
|
T25 |
46282 |
|
T26 |
1844 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2567668 |
1 |
|
|
T24 |
18 |
|
T25 |
20633 |
|
T26 |
780 |
| auto[1] |
auto[0] |
auto[1] |
378636 |
1 |
|
|
T25 |
2688 |
|
T26 |
176 |
|
T29 |
7717 |
| auto[1] |
auto[1] |
auto[0] |
2520292 |
1 |
|
|
T24 |
6 |
|
T25 |
20149 |
|
T26 |
710 |
| auto[1] |
auto[1] |
auto[1] |
369928 |
1 |
|
|
T25 |
2812 |
|
T26 |
178 |
|
T29 |
8492 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7794114 |
1 |
|
|
T23 |
1 |
|
T24 |
97 |
|
T25 |
57272 |
| auto[1] |
5852449 |
1 |
|
|
T24 |
24 |
|
T25 |
46890 |
|
T26 |
1689 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12901054 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98666 |
| auto[1] |
745509 |
1 |
|
|
T24 |
1 |
|
T25 |
5496 |
|
T26 |
284 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7823701 |
1 |
|
|
T23 |
1 |
|
T24 |
84 |
|
T25 |
57899 |
| auto[1] |
5822862 |
1 |
|
|
T24 |
37 |
|
T25 |
46263 |
|
T26 |
1565 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2544440 |
1 |
|
|
T24 |
24 |
|
T25 |
21324 |
|
T26 |
623 |
| auto[1] |
auto[0] |
auto[1] |
374095 |
1 |
|
|
T25 |
2854 |
|
T26 |
147 |
|
T29 |
7702 |
| auto[1] |
auto[1] |
auto[0] |
2532913 |
1 |
|
|
T24 |
12 |
|
T25 |
19443 |
|
T26 |
658 |
| auto[1] |
auto[1] |
auto[1] |
371414 |
1 |
|
|
T24 |
1 |
|
T25 |
2642 |
|
T26 |
137 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7770199 |
1 |
|
|
T23 |
1 |
|
T24 |
99 |
|
T25 |
56919 |
| auto[1] |
5876364 |
1 |
|
|
T24 |
22 |
|
T25 |
47243 |
|
T26 |
1862 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12892697 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98459 |
| auto[1] |
753866 |
1 |
|
|
T24 |
2 |
|
T25 |
5703 |
|
T26 |
320 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7785924 |
1 |
|
|
T23 |
1 |
|
T24 |
95 |
|
T25 |
57452 |
| auto[1] |
5860639 |
1 |
|
|
T24 |
26 |
|
T25 |
46710 |
|
T26 |
1666 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2534894 |
1 |
|
|
T24 |
16 |
|
T25 |
19814 |
|
T26 |
499 |
| auto[1] |
auto[0] |
auto[1] |
373504 |
1 |
|
|
T24 |
2 |
|
T25 |
2761 |
|
T26 |
123 |
| auto[1] |
auto[1] |
auto[0] |
2571879 |
1 |
|
|
T24 |
8 |
|
T25 |
21193 |
|
T26 |
847 |
| auto[1] |
auto[1] |
auto[1] |
380362 |
1 |
|
|
T25 |
2942 |
|
T26 |
197 |
|
T29 |
7829 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7798916 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
56655 |
| auto[1] |
5847647 |
1 |
|
|
T24 |
18 |
|
T25 |
47507 |
|
T26 |
1765 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12902341 |
1 |
|
|
T23 |
1 |
|
T24 |
118 |
|
T25 |
98484 |
| auto[1] |
744222 |
1 |
|
|
T24 |
3 |
|
T25 |
5678 |
|
T26 |
347 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7826276 |
1 |
|
|
T23 |
1 |
|
T24 |
86 |
|
T25 |
56674 |
| auto[1] |
5820287 |
1 |
|
|
T24 |
35 |
|
T25 |
47488 |
|
T26 |
1816 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2533348 |
1 |
|
|
T24 |
31 |
|
T25 |
20613 |
|
T26 |
638 |
| auto[1] |
auto[0] |
auto[1] |
371679 |
1 |
|
|
T24 |
3 |
|
T25 |
2843 |
|
T26 |
147 |
| auto[1] |
auto[1] |
auto[0] |
2542717 |
1 |
|
|
T24 |
1 |
|
T25 |
21197 |
|
T26 |
831 |
| auto[1] |
auto[1] |
auto[1] |
372543 |
1 |
|
|
T25 |
2835 |
|
T26 |
200 |
|
T29 |
7321 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7811856 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
57824 |
| auto[1] |
5834707 |
1 |
|
|
T24 |
18 |
|
T25 |
46338 |
|
T26 |
1625 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897548 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98506 |
| auto[1] |
749015 |
1 |
|
|
T24 |
1 |
|
T25 |
5656 |
|
T26 |
278 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7808132 |
1 |
|
|
T23 |
1 |
|
T24 |
95 |
|
T25 |
57538 |
| auto[1] |
5838431 |
1 |
|
|
T24 |
26 |
|
T25 |
46624 |
|
T26 |
1433 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2551884 |
1 |
|
|
T24 |
22 |
|
T25 |
20655 |
|
T26 |
634 |
| auto[1] |
auto[0] |
auto[1] |
374317 |
1 |
|
|
T24 |
1 |
|
T25 |
2865 |
|
T26 |
152 |
| auto[1] |
auto[1] |
auto[0] |
2537532 |
1 |
|
|
T24 |
3 |
|
T25 |
20313 |
|
T26 |
521 |
| auto[1] |
auto[1] |
auto[1] |
374698 |
1 |
|
|
T25 |
2791 |
|
T26 |
126 |
|
T29 |
7818 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7811430 |
1 |
|
|
T23 |
1 |
|
T24 |
91 |
|
T25 |
57792 |
| auto[1] |
5835133 |
1 |
|
|
T24 |
30 |
|
T25 |
46370 |
|
T26 |
1782 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12905172 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98328 |
| auto[1] |
741391 |
1 |
|
|
T24 |
1 |
|
T25 |
5834 |
|
T26 |
328 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7845843 |
1 |
|
|
T23 |
1 |
|
T24 |
107 |
|
T25 |
56545 |
| auto[1] |
5800720 |
1 |
|
|
T24 |
14 |
|
T25 |
47617 |
|
T26 |
1653 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2529226 |
1 |
|
|
T24 |
6 |
|
T25 |
21606 |
|
T26 |
625 |
| auto[1] |
auto[0] |
auto[1] |
370720 |
1 |
|
|
T25 |
3129 |
|
T26 |
155 |
|
T29 |
8282 |
| auto[1] |
auto[1] |
auto[0] |
2530103 |
1 |
|
|
T24 |
7 |
|
T25 |
20177 |
|
T26 |
700 |
| auto[1] |
auto[1] |
auto[1] |
370671 |
1 |
|
|
T24 |
1 |
|
T25 |
2705 |
|
T26 |
173 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7816171 |
1 |
|
|
T23 |
1 |
|
T24 |
115 |
|
T25 |
57905 |
| auto[1] |
5830392 |
1 |
|
|
T24 |
6 |
|
T25 |
46257 |
|
T26 |
1427 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898884 |
1 |
|
|
T23 |
1 |
|
T24 |
118 |
|
T25 |
98456 |
| auto[1] |
747679 |
1 |
|
|
T24 |
3 |
|
T25 |
5706 |
|
T26 |
280 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7813359 |
1 |
|
|
T23 |
1 |
|
T24 |
78 |
|
T25 |
57963 |
| auto[1] |
5833204 |
1 |
|
|
T24 |
43 |
|
T25 |
46199 |
|
T26 |
1526 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2547635 |
1 |
|
|
T24 |
34 |
|
T25 |
20632 |
|
T26 |
663 |
| auto[1] |
auto[0] |
auto[1] |
375100 |
1 |
|
|
T24 |
3 |
|
T25 |
2919 |
|
T26 |
146 |
| auto[1] |
auto[1] |
auto[0] |
2537890 |
1 |
|
|
T24 |
6 |
|
T25 |
19861 |
|
T26 |
583 |
| auto[1] |
auto[1] |
auto[1] |
372579 |
1 |
|
|
T25 |
2787 |
|
T26 |
134 |
|
T29 |
7180 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7790924 |
1 |
|
|
T23 |
1 |
|
T24 |
89 |
|
T25 |
58865 |
| auto[1] |
5855639 |
1 |
|
|
T24 |
32 |
|
T25 |
45297 |
|
T26 |
1479 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12900004 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98652 |
| auto[1] |
746559 |
1 |
|
|
T24 |
2 |
|
T25 |
5510 |
|
T26 |
297 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7822946 |
1 |
|
|
T23 |
1 |
|
T24 |
104 |
|
T25 |
57610 |
| auto[1] |
5823617 |
1 |
|
|
T24 |
17 |
|
T25 |
46552 |
|
T26 |
1515 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2536818 |
1 |
|
|
T24 |
9 |
|
T25 |
21993 |
|
T26 |
674 |
| auto[1] |
auto[0] |
auto[1] |
372348 |
1 |
|
|
T24 |
1 |
|
T25 |
2942 |
|
T26 |
156 |
| auto[1] |
auto[1] |
auto[0] |
2540240 |
1 |
|
|
T24 |
6 |
|
T25 |
19049 |
|
T26 |
544 |
| auto[1] |
auto[1] |
auto[1] |
374211 |
1 |
|
|
T24 |
1 |
|
T25 |
2568 |
|
T26 |
141 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7787130 |
1 |
|
|
T23 |
1 |
|
T24 |
107 |
|
T25 |
56180 |
| auto[1] |
5859433 |
1 |
|
|
T24 |
14 |
|
T25 |
47982 |
|
T26 |
1959 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12895592 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98464 |
| auto[1] |
750971 |
1 |
|
|
T24 |
2 |
|
T25 |
5698 |
|
T26 |
324 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7789057 |
1 |
|
|
T23 |
1 |
|
T24 |
89 |
|
T25 |
56934 |
| auto[1] |
5857506 |
1 |
|
|
T24 |
32 |
|
T25 |
47228 |
|
T26 |
1697 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2546481 |
1 |
|
|
T24 |
17 |
|
T25 |
20323 |
|
T26 |
500 |
| auto[1] |
auto[0] |
auto[1] |
373908 |
1 |
|
|
T24 |
2 |
|
T25 |
2771 |
|
T26 |
113 |
| auto[1] |
auto[1] |
auto[0] |
2560054 |
1 |
|
|
T24 |
13 |
|
T25 |
21207 |
|
T26 |
873 |
| auto[1] |
auto[1] |
auto[1] |
377063 |
1 |
|
|
T25 |
2927 |
|
T26 |
211 |
|
T29 |
8198 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7790248 |
1 |
|
|
T23 |
1 |
|
T24 |
109 |
|
T25 |
59827 |
| auto[1] |
5856315 |
1 |
|
|
T24 |
12 |
|
T25 |
44335 |
|
T26 |
1829 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12899777 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98678 |
| auto[1] |
746786 |
1 |
|
|
T24 |
1 |
|
T25 |
5484 |
|
T26 |
273 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7811238 |
1 |
|
|
T23 |
1 |
|
T24 |
88 |
|
T25 |
58783 |
| auto[1] |
5835325 |
1 |
|
|
T24 |
33 |
|
T25 |
45379 |
|
T26 |
1482 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2540867 |
1 |
|
|
T24 |
29 |
|
T25 |
21171 |
|
T26 |
482 |
| auto[1] |
auto[0] |
auto[1] |
372335 |
1 |
|
|
T24 |
1 |
|
T25 |
2944 |
|
T26 |
105 |
| auto[1] |
auto[1] |
auto[0] |
2547672 |
1 |
|
|
T24 |
3 |
|
T25 |
18724 |
|
T26 |
727 |
| auto[1] |
auto[1] |
auto[1] |
374451 |
1 |
|
|
T25 |
2540 |
|
T26 |
168 |
|
T29 |
7674 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7815887 |
1 |
|
|
T23 |
1 |
|
T24 |
109 |
|
T25 |
56648 |
| auto[1] |
5830676 |
1 |
|
|
T24 |
12 |
|
T25 |
47514 |
|
T26 |
1280 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12900022 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98368 |
| auto[1] |
746541 |
1 |
|
|
T24 |
1 |
|
T25 |
5794 |
|
T26 |
322 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7816559 |
1 |
|
|
T23 |
1 |
|
T24 |
106 |
|
T25 |
57729 |
| auto[1] |
5830004 |
1 |
|
|
T24 |
15 |
|
T25 |
46433 |
|
T26 |
1693 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2552331 |
1 |
|
|
T24 |
14 |
|
T25 |
20622 |
|
T26 |
771 |
| auto[1] |
auto[0] |
auto[1] |
375396 |
1 |
|
|
T24 |
1 |
|
T25 |
2853 |
|
T26 |
185 |
| auto[1] |
auto[1] |
auto[0] |
2531132 |
1 |
|
|
T25 |
20017 |
|
T26 |
600 |
|
T29 |
53033 |
| auto[1] |
auto[1] |
auto[1] |
371145 |
1 |
|
|
T25 |
2941 |
|
T26 |
137 |
|
T29 |
7661 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7824296 |
1 |
|
|
T23 |
1 |
|
T24 |
105 |
|
T25 |
59233 |
| auto[1] |
5822267 |
1 |
|
|
T24 |
16 |
|
T25 |
44929 |
|
T26 |
1884 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12899171 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98285 |
| auto[1] |
747392 |
1 |
|
|
T24 |
2 |
|
T25 |
5877 |
|
T26 |
284 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7809320 |
1 |
|
|
T23 |
1 |
|
T24 |
96 |
|
T25 |
56429 |
| auto[1] |
5837243 |
1 |
|
|
T24 |
25 |
|
T25 |
47733 |
|
T26 |
1447 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2551675 |
1 |
|
|
T24 |
19 |
|
T25 |
22103 |
|
T26 |
591 |
| auto[1] |
auto[0] |
auto[1] |
374409 |
1 |
|
|
T24 |
2 |
|
T25 |
3083 |
|
T26 |
146 |
| auto[1] |
auto[1] |
auto[0] |
2538176 |
1 |
|
|
T24 |
4 |
|
T25 |
19753 |
|
T26 |
572 |
| auto[1] |
auto[1] |
auto[1] |
372983 |
1 |
|
|
T25 |
2794 |
|
T26 |
138 |
|
T29 |
7903 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7808239 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
55696 |
| auto[1] |
5838324 |
1 |
|
|
T24 |
18 |
|
T25 |
48466 |
|
T26 |
1481 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12900729 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98159 |
| auto[1] |
745834 |
1 |
|
|
T24 |
2 |
|
T25 |
6003 |
|
T26 |
243 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7824355 |
1 |
|
|
T23 |
1 |
|
T24 |
90 |
|
T25 |
55685 |
| auto[1] |
5822208 |
1 |
|
|
T24 |
31 |
|
T25 |
48477 |
|
T26 |
1344 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2555897 |
1 |
|
|
T24 |
21 |
|
T25 |
20527 |
|
T26 |
582 |
| auto[1] |
auto[0] |
auto[1] |
376109 |
1 |
|
|
T24 |
2 |
|
T25 |
2834 |
|
T26 |
127 |
| auto[1] |
auto[1] |
auto[0] |
2520477 |
1 |
|
|
T24 |
8 |
|
T25 |
21947 |
|
T26 |
519 |
| auto[1] |
auto[1] |
auto[1] |
369725 |
1 |
|
|
T25 |
3169 |
|
T26 |
116 |
|
T29 |
7166 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7809387 |
1 |
|
|
T23 |
1 |
|
T24 |
113 |
|
T25 |
55976 |
| auto[1] |
5837176 |
1 |
|
|
T24 |
8 |
|
T25 |
48186 |
|
T26 |
1639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12896945 |
1 |
|
|
T23 |
1 |
|
T24 |
121 |
|
T25 |
98207 |
| auto[1] |
749618 |
1 |
|
|
T25 |
5955 |
|
T26 |
266 |
|
T29 |
16020 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7797461 |
1 |
|
|
T23 |
1 |
|
T24 |
105 |
|
T25 |
56045 |
| auto[1] |
5849102 |
1 |
|
|
T24 |
16 |
|
T25 |
48117 |
|
T26 |
1391 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2542279 |
1 |
|
|
T24 |
16 |
|
T25 |
20506 |
|
T26 |
558 |
| auto[1] |
auto[0] |
auto[1] |
373422 |
1 |
|
|
T25 |
2805 |
|
T26 |
134 |
|
T29 |
7710 |
| auto[1] |
auto[1] |
auto[0] |
2557205 |
1 |
|
|
T25 |
21656 |
|
T26 |
567 |
|
T29 |
56100 |
| auto[1] |
auto[1] |
auto[1] |
376196 |
1 |
|
|
T25 |
3150 |
|
T26 |
132 |
|
T29 |
8310 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7796456 |
1 |
|
|
T23 |
1 |
|
T24 |
109 |
|
T25 |
55762 |
| auto[1] |
5850107 |
1 |
|
|
T24 |
12 |
|
T25 |
48400 |
|
T26 |
1571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898278 |
1 |
|
|
T23 |
1 |
|
T24 |
121 |
|
T25 |
98190 |
| auto[1] |
748285 |
1 |
|
|
T25 |
5972 |
|
T26 |
397 |
|
T29 |
15040 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7805072 |
1 |
|
|
T23 |
1 |
|
T24 |
114 |
|
T25 |
55927 |
| auto[1] |
5841491 |
1 |
|
|
T24 |
7 |
|
T25 |
48235 |
|
T26 |
1960 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2541334 |
1 |
|
|
T24 |
7 |
|
T25 |
20108 |
|
T26 |
739 |
| auto[1] |
auto[0] |
auto[1] |
373772 |
1 |
|
|
T25 |
2769 |
|
T26 |
184 |
|
T29 |
8030 |
| auto[1] |
auto[1] |
auto[0] |
2551872 |
1 |
|
|
T25 |
22155 |
|
T26 |
824 |
|
T29 |
49539 |
| auto[1] |
auto[1] |
auto[1] |
374513 |
1 |
|
|
T25 |
3203 |
|
T26 |
213 |
|
T29 |
7010 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7830016 |
1 |
|
|
T23 |
1 |
|
T24 |
97 |
|
T25 |
58397 |
| auto[1] |
5816547 |
1 |
|
|
T24 |
24 |
|
T25 |
45765 |
|
T26 |
1610 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12891850 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98429 |
| auto[1] |
754713 |
1 |
|
|
T24 |
2 |
|
T25 |
5733 |
|
T26 |
264 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7773200 |
1 |
|
|
T23 |
1 |
|
T24 |
87 |
|
T25 |
56914 |
| auto[1] |
5873363 |
1 |
|
|
T24 |
34 |
|
T25 |
47248 |
|
T26 |
1369 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2570209 |
1 |
|
|
T24 |
19 |
|
T25 |
22007 |
|
T26 |
617 |
| auto[1] |
auto[0] |
auto[1] |
379311 |
1 |
|
|
T24 |
2 |
|
T25 |
3151 |
|
T26 |
141 |
| auto[1] |
auto[1] |
auto[0] |
2548441 |
1 |
|
|
T24 |
13 |
|
T25 |
19508 |
|
T26 |
488 |
| auto[1] |
auto[1] |
auto[1] |
375402 |
1 |
|
|
T25 |
2582 |
|
T26 |
123 |
|
T29 |
7705 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7814230 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
57464 |
| auto[1] |
5832333 |
1 |
|
|
T24 |
18 |
|
T25 |
46698 |
|
T26 |
1446 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12896104 |
1 |
|
|
T23 |
1 |
|
T24 |
118 |
|
T25 |
99002 |
| auto[1] |
750459 |
1 |
|
|
T24 |
3 |
|
T25 |
5160 |
|
T26 |
239 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7791351 |
1 |
|
|
T23 |
1 |
|
T24 |
81 |
|
T25 |
60408 |
| auto[1] |
5855212 |
1 |
|
|
T24 |
40 |
|
T25 |
43754 |
|
T26 |
1193 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2570807 |
1 |
|
|
T24 |
29 |
|
T25 |
20206 |
|
T26 |
486 |
| auto[1] |
auto[0] |
auto[1] |
377417 |
1 |
|
|
T24 |
3 |
|
T25 |
2683 |
|
T26 |
127 |
| auto[1] |
auto[1] |
auto[0] |
2533946 |
1 |
|
|
T24 |
8 |
|
T25 |
18388 |
|
T26 |
468 |
| auto[1] |
auto[1] |
auto[1] |
373042 |
1 |
|
|
T25 |
2477 |
|
T26 |
112 |
|
T29 |
7592 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7859240 |
1 |
|
|
T23 |
1 |
|
T24 |
105 |
|
T25 |
58763 |
| auto[1] |
5787323 |
1 |
|
|
T24 |
16 |
|
T25 |
45399 |
|
T26 |
1290 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898147 |
1 |
|
|
T23 |
1 |
|
T24 |
118 |
|
T25 |
98428 |
| auto[1] |
748416 |
1 |
|
|
T24 |
3 |
|
T25 |
5734 |
|
T26 |
300 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7812917 |
1 |
|
|
T23 |
1 |
|
T24 |
90 |
|
T25 |
57149 |
| auto[1] |
5833646 |
1 |
|
|
T24 |
31 |
|
T25 |
47013 |
|
T26 |
1506 |