Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7778813 |
1 |
|
|
T23 |
1 |
|
T24 |
109 |
|
T25 |
56668 |
| auto[1] |
5867750 |
1 |
|
|
T24 |
12 |
|
T25 |
47494 |
|
T26 |
1429 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897206 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98575 |
| auto[1] |
749357 |
1 |
|
|
T24 |
1 |
|
T25 |
5587 |
|
T26 |
358 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7803975 |
1 |
|
|
T23 |
1 |
|
T24 |
94 |
|
T25 |
58374 |
| auto[1] |
5842588 |
1 |
|
|
T24 |
27 |
|
T25 |
45788 |
|
T26 |
1822 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2541009 |
1 |
|
|
T24 |
24 |
|
T25 |
18541 |
|
T26 |
730 |
| auto[1] |
auto[0] |
auto[1] |
372938 |
1 |
|
|
T25 |
2513 |
|
T26 |
182 |
|
T29 |
7835 |
| auto[1] |
auto[1] |
auto[0] |
2552222 |
1 |
|
|
T24 |
2 |
|
T25 |
21660 |
|
T26 |
734 |
| auto[1] |
auto[1] |
auto[1] |
376419 |
1 |
|
|
T24 |
1 |
|
T25 |
3074 |
|
T26 |
176 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |