Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7796022 |
1 |
|
|
T23 |
1 |
|
T24 |
109 |
|
T25 |
59436 |
| auto[1] |
5850541 |
1 |
|
|
T24 |
12 |
|
T25 |
44726 |
|
T26 |
1835 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897339 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98639 |
| auto[1] |
749224 |
1 |
|
|
T24 |
1 |
|
T25 |
5523 |
|
T26 |
333 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7802888 |
1 |
|
|
T23 |
1 |
|
T24 |
99 |
|
T25 |
58805 |
| auto[1] |
5843675 |
1 |
|
|
T24 |
22 |
|
T25 |
45357 |
|
T26 |
1749 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2537787 |
1 |
|
|
T24 |
21 |
|
T25 |
20407 |
|
T26 |
625 |
| auto[1] |
auto[0] |
auto[1] |
372546 |
1 |
|
|
T24 |
1 |
|
T25 |
2854 |
|
T26 |
149 |
| auto[1] |
auto[1] |
auto[0] |
2556664 |
1 |
|
|
T25 |
19427 |
|
T26 |
791 |
|
T29 |
51287 |
| auto[1] |
auto[1] |
auto[1] |
376678 |
1 |
|
|
T25 |
2669 |
|
T26 |
184 |
|
T29 |
7476 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |